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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9865853851
Add QUICC Engine (QE) configuration, header files, and QE management and library code that are used by QE devices drivers. Includes Leo's modifications up to, and including, the platform_device to of_device adaptation: "The series of patches add generic QE infrastructure called qe_lib, and MPC8360EMDS board support. Qe_lib is used by QE device drivers such as ucc_geth driver. This version updates QE interrupt controller to use new irq mapping mechanism, addresses all the comments received with last submission and includes some style fixes. v2: Change to use device tree for BCSR and MURAM; Remove I/O port interrupt handling code as it is not generic enough. v3: Address comments from Kumar; Update definition of several device tree nodes; Copyright style change." In addition, the following changes have been made: o removed typedefs o uint -> u32 conversions o removed following defines: QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER, BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET because they hid sizeof/in_be32/out_be32 operations from the reader. o fixed qe_snums_init() serial num assignment to use a const array o made CONFIG_UCC_FAST select UCC_SLOW o reduced NR_QE_IC_INTS from 128 to 64 o remove _IO_BASE, etc. defines (not used) o removed irrelevant comments, added others to resemble removed BD_ defines o realigned struct definitions in headers o various other style fixes including things like pinMask -> pin_mask o fixed a ton of whitespace issues o marked ioregs as __be32/__be16 o removed platform_device code and redundant get_qe_base() o removed redundant comments o added cpu_relax() to qe_reset o uncasted all get_property() assignments o eliminated unneeded casts o eliminated immrbar_phys_to_virt (not used) Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Shlomi Gridish <gridish@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
163 lines
4.5 KiB
C
163 lines
4.5 KiB
C
/*
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* include/linux/fsl_devices.h
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*
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* Definitions for any platform device related flags or structures for
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* Freescale processor devices
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef _FSL_DEVICE_H_
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#define _FSL_DEVICE_H_
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#include <linux/types.h>
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/*
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* Some conventions on how we handle peripherals on Freescale chips
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*
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* unique device: a platform_device entry in fsl_plat_devs[] plus
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* associated device information in its platform_data structure.
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*
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* A chip is described by a set of unique devices.
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*
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* Each sub-arch has its own master list of unique devices and
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* enumerates them by enum fsl_devices in a sub-arch specific header
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*
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* The platform data structure is broken into two parts. The
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* first is device specific information that help identify any
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* unique features of a peripheral. The second is any
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* information that may be defined by the board or how the device
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* is connected externally of the chip.
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*
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* naming conventions:
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* - platform data structures: <driver>_platform_data
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* - platform data device flags: FSL_<driver>_DEV_<FLAG>
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* - platform data board flags: FSL_<driver>_BRD_<FLAG>
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*
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*/
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struct gianfar_platform_data {
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/* device specific information */
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u32 device_flags;
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/* board specific information */
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u32 board_flags;
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u32 bus_id;
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u32 phy_id;
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u8 mac_addr[6];
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};
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struct gianfar_mdio_data {
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/* board specific information */
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int irq[32];
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};
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/* Flags related to gianfar device features */
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#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
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#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
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#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
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#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
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#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
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#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
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#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
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#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
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/* Flags in gianfar_platform_data */
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#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */
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#define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */
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struct fsl_i2c_platform_data {
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/* device specific information */
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u32 device_flags;
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};
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/* Flags related to I2C device features */
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#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
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#define FSL_I2C_DEV_CLOCK_5200 0x00000002
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enum fsl_usb2_operating_modes {
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FSL_USB2_MPH_HOST,
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FSL_USB2_DR_HOST,
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FSL_USB2_DR_DEVICE,
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FSL_USB2_DR_OTG,
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};
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enum fsl_usb2_phy_modes {
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FSL_USB2_PHY_NONE,
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FSL_USB2_PHY_ULPI,
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FSL_USB2_PHY_UTMI,
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FSL_USB2_PHY_UTMI_WIDE,
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FSL_USB2_PHY_SERIAL,
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};
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struct fsl_usb2_platform_data {
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/* board specific information */
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enum fsl_usb2_operating_modes operating_mode;
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enum fsl_usb2_phy_modes phy_mode;
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unsigned int port_enables;
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};
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/* Flags in fsl_usb2_mph_platform_data */
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#define FSL_USB2_PORT0_ENABLED 0x00000001
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#define FSL_USB2_PORT1_ENABLED 0x00000002
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struct fsl_spi_platform_data {
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u32 initial_spmode; /* initial SPMODE value */
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u16 bus_num;
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/* board specific information */
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u16 max_chipselect;
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void (*activate_cs)(u8 cs, u8 polarity);
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void (*deactivate_cs)(u8 cs, u8 polarity);
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u32 sysclk;
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};
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/* Ethernet interface (phy management and speed)
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*/
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enum enet_interface {
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ENET_10_MII, /* 10 Base T, MII interface */
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ENET_10_RMII, /* 10 Base T, RMII interface */
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ENET_10_RGMII, /* 10 Base T, RGMII interface */
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ENET_100_MII, /* 100 Base T, MII interface */
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ENET_100_RMII, /* 100 Base T, RMII interface */
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ENET_100_RGMII, /* 100 Base T, RGMII interface */
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ENET_1000_GMII, /* 1000 Base T, GMII interface */
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ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
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ENET_1000_TBI, /* 1000 Base T, TBI interface */
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ENET_1000_RTBI /* 1000 Base T, RTBI interface */
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};
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struct ucc_geth_platform_data {
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/* device specific information */
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u32 device_flags;
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u32 phy_reg_addr;
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/* board specific information */
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u32 board_flags;
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u8 rx_clock;
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u8 tx_clock;
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u32 phy_id;
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enum enet_interface phy_interface;
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u32 phy_interrupt;
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u8 mac_addr[6];
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};
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/* Flags related to UCC Gigabit Ethernet device features */
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#define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001
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#define FSL_UGETH_DEV_HAS_COALESCE 0x00000002
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#define FSL_UGETH_DEV_HAS_RMON 0x00000004
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/* Flags in ucc_geth_platform_data */
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#define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001
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/* if not set use a timer */
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#endif /* _FSL_DEVICE_H_ */
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#endif /* __KERNEL__ */
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