mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* include/asm-v850/teg.h -- NB85E-TEG cpu chip
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_TEG_H__
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#define __V850_TEG_H__
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/* The TEG uses the V850E cpu core. */
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#include <asm/v850e.h>
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#include <asm/v850e_cache.h>
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#define CPU_MODEL "v850e/nb85e-teg"
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#define CPU_MODEL_LONG "NEC V850E/NB85E TEG"
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/* For <asm/entry.h> */
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/* We use on-chip RAM, for a few miscellaneous variables that must be
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accessible using a load instruction relative to R0. On the NB85E/TEG,
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There's 60KB of iRAM starting at 0xFFFF0000, however we need the base
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address to be addressable by a 16-bit signed offset, so we only use the
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second half of it starting from 0xFFFF8000. */
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#define R0_RAM_ADDR 0xFFFF8000
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/* Hardware-specific interrupt numbers (in the kernel IRQ namespace).
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Some of these are parameterized even though there's only a single
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interrupt, for compatibility with some generic code that works on other
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processor models. */
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#define IRQ_INTCMD(n) 6 /* interval timer interrupt */
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#define IRQ_INTCMD_NUM 1
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#define IRQ_INTSER(n) 16 /* UART reception error */
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#define IRQ_INTSER_NUM 1
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#define IRQ_INTSR(n) 17 /* UART reception completion */
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#define IRQ_INTSR_NUM 1
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#define IRQ_INTST(n) 18 /* UART transmission completion */
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#define IRQ_INTST_NUM 1
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/* For <asm/irq.h> */
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#define NUM_CPU_IRQS 64
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/* TEG UART details. */
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#define V850E_UART_BASE_ADDR(n) (0xFFFFF600 + 0x10 * (n))
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#define V850E_UART_ASIM_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x0)
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#define V850E_UART_ASIS_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x2)
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#define V850E_UART_ASIF_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x4)
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#define V850E_UART_CKSR_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x6)
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#define V850E_UART_BRGC_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x8)
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#define V850E_UART_TXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0xA)
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#define V850E_UART_RXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0xC)
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#define V850E_UART_NUM_CHANNELS 1
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#define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
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/* This is a function that gets called before configuring the UART. */
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#define V850E_UART_PRE_CONFIGURE teg_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void teg_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* The TEG RTPU. */
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#define V850E_RTPU_BASE_ADDR 0xFFFFF210
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/* TEG series timer D details. */
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#define V850E_TIMER_D_BASE_ADDR 0xFFFFF210
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#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
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#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
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#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x8)
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#define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
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/* `Interrupt Source Select' control register. */
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#define TEG_ISS_ADDR 0xFFFFF7FA
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#define TEG_ISS (*(volatile u8 *)TEG_ISS_ADDR)
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/* Port 0 I/O register (bits 0-3 used). */
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#define TEG_PORT0_IO_ADDR 0xFFFFF7F2
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#define TEG_PORT0_IO (*(volatile u8 *)TEG_PORT0_IO_ADDR)
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/* Port 0 control register (bits 0-3 control mode, 0 = output, 1 = input). */
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#define TEG_PORT0_PM_ADDR 0xFFFFF7F4
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#define TEG_PORT0_PM (*(volatile u8 *)TEG_PORT0_PM_ADDR)
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#ifndef __ASSEMBLY__
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extern void teg_init_irqs (void);
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#endif
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#endif /* __V850_TEG_H__ */
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