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This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
#ifndef _BLACKFIN_DELAY_H
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#define _BLACKFIN_DELAY_H
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static inline void __delay(unsigned long loops)
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{
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/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
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uncomment this as soon those are implemented */
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/*
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__asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t"
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"1:\t NOP;\n\t"
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: :"a" (loops)
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: "LT0","LB0","LC0");
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*/
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__asm__ __volatile__("[--SP] = LC0;\n\t"
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"[--SP] = LT0;\n\t"
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"[--SP] = LB0;\n\t"
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"LSETUP (1f,1f) LC0 = %0;\n\t"
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"1:\t NOP;\n\t"
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"LB0 = [SP++];\n\t"
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"LT0 = [SP++];\n\t"
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"LC0 = [SP++];\n"
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:
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:"a" (loops));
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}
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#include <linux/param.h> /* needed for HZ */
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/*
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* Use only for very small delays ( < 1 msec). Should probably use a
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* lookup table, really, as the multiplications take much too long with
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* short delays. This is a "reasonable" implementation, though (and the
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* first constant multiplications gets optimized away if the delay is
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* a constant)
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*/
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static inline void udelay(unsigned long usecs)
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{
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extern unsigned long loops_per_jiffy;
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__delay(usecs * loops_per_jiffy / (1000000 / HZ));
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}
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#endif /* defined(_BLACKFIN_DELAY_H) */
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