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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
48 lines
1.9 KiB
Plaintext
48 lines
1.9 KiB
Plaintext
On some platforms, so-called memory-mapped I/O is weakly ordered. On such
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platforms, driver writers are responsible for ensuring that I/O writes to
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memory-mapped addresses on their device arrive in the order intended. This is
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typically done by reading a 'safe' device or bridge register, causing the I/O
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chipset to flush pending writes to the device before any reads are posted. A
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driver would usually use this technique immediately prior to the exit of a
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critical section of code protected by spinlocks. This would ensure that
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subsequent writes to I/O space arrived only after all prior writes (much like a
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memory barrier op, mb(), only with respect to I/O).
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A more concrete example from a hypothetical device driver:
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...
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CPU A: spin_lock_irqsave(&dev_lock, flags)
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CPU A: val = readl(my_status);
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CPU A: ...
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CPU A: writel(newval, ring_ptr);
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CPU A: spin_unlock_irqrestore(&dev_lock, flags)
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...
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CPU B: spin_lock_irqsave(&dev_lock, flags)
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CPU B: val = readl(my_status);
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CPU B: ...
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CPU B: writel(newval2, ring_ptr);
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CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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...
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In the case above, the device may receive newval2 before it receives newval,
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which could cause problems. Fixing it is easy enough though:
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...
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CPU A: spin_lock_irqsave(&dev_lock, flags)
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CPU A: val = readl(my_status);
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CPU A: ...
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CPU A: writel(newval, ring_ptr);
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CPU A: (void)readl(safe_register); /* maybe a config register? */
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CPU A: spin_unlock_irqrestore(&dev_lock, flags)
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...
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CPU B: spin_lock_irqsave(&dev_lock, flags)
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CPU B: val = readl(my_status);
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CPU B: ...
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CPU B: writel(newval2, ring_ptr);
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CPU B: (void)readl(safe_register); /* maybe a config register? */
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CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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Here, the reads from safe_register will cause the I/O chipset to flush any
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pending writes before actually posting the read to the chipset, preventing
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possible data corruption.
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