mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 14:46:47 +07:00
4ccf4beab8
MX23/28 use IP cores which follow a register layout I have first seen on
STMP3xxx SoCs. In this layout, every register actually has four u32:
1.) to store a value directly
2.) a SET register where every 1-bit sets the corresponding bit,
others are unaffected
3.) same with a CLR register
4.) same with a TOG (toggle) register
Also, the 2 MSBs in register 0 are always the same and can be used to reset
the IP core.
All this is strictly speaking not mach-specific (but IP core specific) and,
thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
following this stmp-style. So:
Introduce a stmp-style device, put the code and defines for that in a public
place (lib/), and let drivers for stmp-style devices select that code.
To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.
Voila, mach dependency gone, reusable code introduced. Note that I didn't
remove the duplicated code from mach-mxs yet, first the drivers have to be
converted.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/*
|
|
* Copyright (C) 1999 ARM Limited
|
|
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
|
* Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
|
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
|
* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
|
|
* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/module.h>
|
|
#include <linux/stmp_device.h>
|
|
|
|
#define STMP_MODULE_CLKGATE (1 << 30)
|
|
#define STMP_MODULE_SFTRST (1 << 31)
|
|
|
|
/*
|
|
* Clear the bit and poll it cleared. This is usually called with
|
|
* a reset address and mask being either SFTRST(bit 31) or CLKGATE
|
|
* (bit 30).
|
|
*/
|
|
static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
|
|
{
|
|
int timeout = 0x400;
|
|
|
|
writel(mask, addr + STMP_OFFSET_REG_CLR);
|
|
udelay(1);
|
|
while ((readl(addr) & mask) && --timeout)
|
|
/* nothing */;
|
|
|
|
return !timeout;
|
|
}
|
|
|
|
int stmp_reset_block(void __iomem *reset_addr)
|
|
{
|
|
int ret;
|
|
int timeout = 0x400;
|
|
|
|
/* clear and poll SFTRST */
|
|
ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
|
|
if (unlikely(ret))
|
|
goto error;
|
|
|
|
/* clear CLKGATE */
|
|
writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
|
|
|
|
/* set SFTRST to reset the block */
|
|
writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
|
|
udelay(1);
|
|
|
|
/* poll CLKGATE becoming set */
|
|
while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
|
|
/* nothing */;
|
|
if (unlikely(!timeout))
|
|
goto error;
|
|
|
|
/* clear and poll SFTRST */
|
|
ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
|
|
if (unlikely(ret))
|
|
goto error;
|
|
|
|
/* clear and poll CLKGATE */
|
|
ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
|
|
if (unlikely(ret))
|
|
goto error;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
|
|
return -ETIMEDOUT;
|
|
}
|
|
EXPORT_SYMBOL(stmp_reset_block);
|