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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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737b513b4c
According to the datasheet of the panel, both data, DEN and sync signals are expected to be driven on the falling edge of the DOTCLK. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
483 lines
12 KiB
C
483 lines
12 KiB
C
/*
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* Toppoly TD028TTEC1 panel support
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*
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* Copyright (C) 2008 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Neo 1973 code (jbt6k74.c):
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* Copyright (C) 2006-2007 by OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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*
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* Ported and adapted from Neo 1973 U-Boot by:
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* H. Nikolaus Schaller <hns@goldelico.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include "../dss/omapdss.h"
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struct panel_drv_data {
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struct omap_dss_device dssdev;
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struct omap_dss_device *in;
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int data_lines;
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struct videomode vm;
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struct spi_device *spi_dev;
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};
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static struct videomode td028ttec1_panel_vm = {
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.hactive = 480,
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.vactive = 640,
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.pixelclock = 22153000,
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.hfront_porch = 24,
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.hsync_len = 8,
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.hback_porch = 8,
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.vfront_porch = 4,
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.vsync_len = 2,
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.vback_porch = 2,
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.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
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DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
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DISPLAY_FLAGS_PIXDATA_NEGEDGE,
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/*
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* Note: According to the panel documentation:
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* SYNC needs to be driven on the FALLING edge
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*/
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};
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#define JBT_COMMAND 0x000
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#define JBT_DATA 0x100
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static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
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{
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int rc;
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u16 tx_buf = JBT_COMMAND | reg;
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rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
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1*sizeof(u16));
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if (rc != 0)
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dev_err(&ddata->spi_dev->dev,
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"jbt_ret_write_0 spi_write ret %d\n", rc);
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return rc;
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}
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static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
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{
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int rc;
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u16 tx_buf[2];
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tx_buf[0] = JBT_COMMAND | reg;
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tx_buf[1] = JBT_DATA | data;
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rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
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2*sizeof(u16));
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if (rc != 0)
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dev_err(&ddata->spi_dev->dev,
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"jbt_reg_write_1 spi_write ret %d\n", rc);
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return rc;
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}
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static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
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{
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int rc;
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u16 tx_buf[3];
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tx_buf[0] = JBT_COMMAND | reg;
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tx_buf[1] = JBT_DATA | (data >> 8);
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tx_buf[2] = JBT_DATA | (data & 0xff);
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rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
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3*sizeof(u16));
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if (rc != 0)
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dev_err(&ddata->spi_dev->dev,
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"jbt_reg_write_2 spi_write ret %d\n", rc);
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return rc;
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}
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enum jbt_register {
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JBT_REG_SLEEP_IN = 0x10,
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JBT_REG_SLEEP_OUT = 0x11,
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JBT_REG_DISPLAY_OFF = 0x28,
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JBT_REG_DISPLAY_ON = 0x29,
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JBT_REG_RGB_FORMAT = 0x3a,
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JBT_REG_QUAD_RATE = 0x3b,
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JBT_REG_POWER_ON_OFF = 0xb0,
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JBT_REG_BOOSTER_OP = 0xb1,
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JBT_REG_BOOSTER_MODE = 0xb2,
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JBT_REG_BOOSTER_FREQ = 0xb3,
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JBT_REG_OPAMP_SYSCLK = 0xb4,
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JBT_REG_VSC_VOLTAGE = 0xb5,
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JBT_REG_VCOM_VOLTAGE = 0xb6,
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JBT_REG_EXT_DISPL = 0xb7,
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JBT_REG_OUTPUT_CONTROL = 0xb8,
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JBT_REG_DCCLK_DCEV = 0xb9,
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JBT_REG_DISPLAY_MODE1 = 0xba,
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JBT_REG_DISPLAY_MODE2 = 0xbb,
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JBT_REG_DISPLAY_MODE = 0xbc,
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JBT_REG_ASW_SLEW = 0xbd,
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JBT_REG_DUMMY_DISPLAY = 0xbe,
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JBT_REG_DRIVE_SYSTEM = 0xbf,
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JBT_REG_SLEEP_OUT_FR_A = 0xc0,
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JBT_REG_SLEEP_OUT_FR_B = 0xc1,
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JBT_REG_SLEEP_OUT_FR_C = 0xc2,
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JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
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JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
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JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
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JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
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JBT_REG_GAMMA1_FINE_1 = 0xc7,
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JBT_REG_GAMMA1_FINE_2 = 0xc8,
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JBT_REG_GAMMA1_INCLINATION = 0xc9,
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JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
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JBT_REG_BLANK_CONTROL = 0xcf,
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JBT_REG_BLANK_TH_TV = 0xd0,
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JBT_REG_CKV_ON_OFF = 0xd1,
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JBT_REG_CKV_1_2 = 0xd2,
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JBT_REG_OEV_TIMING = 0xd3,
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JBT_REG_ASW_TIMING_1 = 0xd4,
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JBT_REG_ASW_TIMING_2 = 0xd5,
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JBT_REG_HCLOCK_VGA = 0xec,
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JBT_REG_HCLOCK_QVGA = 0xed,
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};
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#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
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static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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int r;
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if (omapdss_device_is_connected(dssdev))
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return 0;
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r = in->ops.dpi->connect(in, dssdev);
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if (r)
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return r;
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return 0;
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}
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static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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if (!omapdss_device_is_connected(dssdev))
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return;
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in->ops.dpi->disconnect(in, dssdev);
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}
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static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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int r;
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if (!omapdss_device_is_connected(dssdev))
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return -ENODEV;
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if (omapdss_device_is_enabled(dssdev))
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return 0;
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if (ddata->data_lines)
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in->ops.dpi->set_data_lines(in, ddata->data_lines);
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in->ops.dpi->set_timings(in, &ddata->vm);
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r = in->ops.dpi->enable(in);
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if (r)
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return r;
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dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
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dssdev->state);
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/* three times command zero */
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r |= jbt_ret_write_0(ddata, 0x00);
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usleep_range(1000, 2000);
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r |= jbt_ret_write_0(ddata, 0x00);
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usleep_range(1000, 2000);
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r |= jbt_ret_write_0(ddata, 0x00);
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usleep_range(1000, 2000);
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if (r) {
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dev_warn(dssdev->dev, "transfer error\n");
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goto transfer_err;
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}
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/* deep standby out */
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r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
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/* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
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r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
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/* Quad mode off */
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r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
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/* AVDD on, XVDD on */
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r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
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/* Output control */
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r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
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/* Sleep mode off */
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r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
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/* at this point we have like 50% grey */
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/* initialize register set */
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r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
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r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
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r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
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r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
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r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
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r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
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r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
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r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
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r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
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r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
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r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
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r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
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r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
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/*
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* default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
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* to avoid red / blue flicker
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*/
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r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
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r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
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r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
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r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
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r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
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r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
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r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
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r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
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r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
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r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
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r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
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r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
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r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
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r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
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r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
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r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
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r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
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r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
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r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
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r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
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r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
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r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
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dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
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transfer_err:
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return r ? -EIO : 0;
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}
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static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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if (!omapdss_device_is_enabled(dssdev))
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return;
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dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
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jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
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jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
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jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
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jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
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in->ops.dpi->disable(in);
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dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
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}
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static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
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struct videomode *vm)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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ddata->vm = *vm;
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dssdev->panel.vm = *vm;
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in->ops.dpi->set_timings(in, vm);
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}
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static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
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struct videomode *vm)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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*vm = ddata->vm;
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}
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static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
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struct videomode *vm)
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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return in->ops.dpi->check_timings(in, vm);
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}
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static struct omap_dss_driver td028ttec1_ops = {
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.connect = td028ttec1_panel_connect,
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.disconnect = td028ttec1_panel_disconnect,
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.enable = td028ttec1_panel_enable,
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.disable = td028ttec1_panel_disable,
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.set_timings = td028ttec1_panel_set_timings,
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.get_timings = td028ttec1_panel_get_timings,
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.check_timings = td028ttec1_panel_check_timings,
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};
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static int td028ttec1_probe_of(struct spi_device *spi)
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{
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struct device_node *node = spi->dev.of_node;
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struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
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struct omap_dss_device *in;
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in = omapdss_of_find_source_for_first_ep(node);
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if (IS_ERR(in)) {
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dev_err(&spi->dev, "failed to find video source\n");
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return PTR_ERR(in);
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}
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ddata->in = in;
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return 0;
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}
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static int td028ttec1_panel_probe(struct spi_device *spi)
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{
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struct panel_drv_data *ddata;
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struct omap_dss_device *dssdev;
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int r;
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dev_dbg(&spi->dev, "%s\n", __func__);
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spi->bits_per_word = 9;
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spi->mode = SPI_MODE_3;
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r = spi_setup(spi);
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if (r < 0) {
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dev_err(&spi->dev, "spi_setup failed: %d\n", r);
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return r;
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}
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ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
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if (ddata == NULL)
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return -ENOMEM;
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dev_set_drvdata(&spi->dev, ddata);
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ddata->spi_dev = spi;
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if (!spi->dev.of_node)
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return -ENODEV;
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r = td028ttec1_probe_of(spi);
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if (r)
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return r;
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ddata->vm = td028ttec1_panel_vm;
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dssdev = &ddata->dssdev;
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dssdev->dev = &spi->dev;
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dssdev->driver = &td028ttec1_ops;
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dssdev->type = OMAP_DISPLAY_TYPE_DPI;
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dssdev->owner = THIS_MODULE;
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dssdev->panel.vm = ddata->vm;
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dssdev->phy.dpi.data_lines = ddata->data_lines;
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r = omapdss_register_display(dssdev);
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if (r) {
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dev_err(&spi->dev, "Failed to register panel\n");
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goto err_reg;
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}
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return 0;
|
|
|
|
err_reg:
|
|
omap_dss_put_device(ddata->in);
|
|
return r;
|
|
}
|
|
|
|
static int td028ttec1_panel_remove(struct spi_device *spi)
|
|
{
|
|
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
|
|
struct omap_dss_device *dssdev = &ddata->dssdev;
|
|
struct omap_dss_device *in = ddata->in;
|
|
|
|
dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
|
|
|
|
omapdss_unregister_display(dssdev);
|
|
|
|
td028ttec1_panel_disable(dssdev);
|
|
td028ttec1_panel_disconnect(dssdev);
|
|
|
|
omap_dss_put_device(in);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id td028ttec1_of_match[] = {
|
|
{ .compatible = "omapdss,toppoly,td028ttec1", },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
|
|
|
|
static struct spi_driver td028ttec1_spi_driver = {
|
|
.probe = td028ttec1_panel_probe,
|
|
.remove = td028ttec1_panel_remove,
|
|
|
|
.driver = {
|
|
.name = "panel-tpo-td028ttec1",
|
|
.of_match_table = td028ttec1_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
module_spi_driver(td028ttec1_spi_driver);
|
|
|
|
MODULE_ALIAS("spi:toppoly,td028ttec1");
|
|
MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
|
|
MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
|
|
MODULE_LICENSE("GPL");
|