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ca36855ef0
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
173 lines
2.7 KiB
Plaintext
173 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada 375 evaluation board
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* (DB-88F6720)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-375.dtsi"
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/ {
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model = "Marvell Armada 375 Development Board";
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compatible = "marvell,a375-db", "marvell,armada375";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
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};
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};
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&pciec {
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status = "okay";
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};
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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&pcie0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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&pcie1 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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&spi0 {
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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/*
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* SPI conflicts with NAND, so we disable it here, and
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* select NAND as the enabled device by default.
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*/
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status = "disabled";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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&uart0 {
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status = "okay";
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};
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&pinctrl {
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sdio_st_pins: sdio-st-pins {
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marvell,pins = "mpp44", "mpp45";
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marvell,function = "gpio";
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};
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};
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&sata {
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status = "okay";
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nr-ports = <2>;
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};
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&nand {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Linux";
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reg = <0x800000 0x800000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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&usb1 {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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&sdio {
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pinctrl-0 = <&sdio_pins &sdio_st_pins>;
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pinctrl-names = "default";
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status = "okay";
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cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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ðernet {
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status = "okay";
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};
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ð0 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ð1 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "gmii";
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};
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