mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 10:18:34 +07:00
43c95d3694
cycle:
Core changes:
- Device links can optionally be added between a pin control
producer and its consumers. This will affect how the system
power management is handled: a pin controller will not suspend
before all of its consumers have been suspended. This was
necessary for the ST Microelectronics STMFX expander and
need to be tested on other systems as well: it makes sense
to make this default in the long run. Right now it is
opt-in per driver.
- Drive strength can be specified in microamps. With decreases
in silicon technology, milliamps isn't granular enough, let's
make it possible to select drive strengths in microamps. Right
now the Meson (AMlogic) driver needs this.
New drivers:
- New subdriver for the Tegra 194 SoC.
- New subdriver for the Qualcomm SDM845.
- New subdriver for the Qualcomm SM8150.
- New subdriver for the Freescale i.MX8MN (Freescale is now a
product line of NXP).
- New subdriver for Marvell MV98DX1135.
Driver improvements:
- The Bitmain BM1880 driver now supports pin config in
addition to muxing.
- The Qualcomm drivers can now reserve some GPIOs as taken
aside and not usable for users. This is used in ACPI systems
to take out some GPIO lines used by the BIOS so that
noone else (neither kernel nor userspace) will play with them
by mistake and crash the machine.
- A slew of refurbishing around the Aspeed drivers (board
management controllers for servers) in preparation for the
new Aspeed AST2600 SoC.
- A slew of improvements over the SH PFC drivers as usual.
- Misc cleanups and fixes.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0oTPcACgkQQRCzN7AZ
XXNTsw//aNPfkJS8gRszv58G56lyuO8h6Cq4m5eDpzhlpjx5qjELgi9h2UNGINqD
7CWxo35ufbKe0fDIcqpXmtuDMtSu6MuKT3SMepuw9uf9wxyndK4RIuyb0lpAJrx2
+NMPxzS+ARlrMmcfvXPRyPWHqAkXsQk6zcCgiuNCPtROkOZgs1YZ3+pemZw2/FMq
gSLTO/95p0TPWr6YAlpByqfsA1A/onEm9HOiU2INV7DrAfUj7mnkuC1nZ4IJDFcv
Gn6qQVQPah+MBzkwt4WXy5kDRozCIbg7x+FQBw3KAO23TrLDTFuNsYIWGFcP2CN2
eT8iSP3cWrXNUuEgcPD59aO07rhFooT+QBQFt2ih1dJCV1u/795wb57nxSh1YDcO
M2tG+AW2EZky65FXwhLW2rq3LvmTM4kiEz3mA/DrcOAKvvQllK+6FKEhNy0StstP
yvvlqoXdgH3sfOnWTAyHr35qA/pMuGEXSryWTJPqpflCvZ3wxNk+IV5nyPAtfaFz
CK7U0Ya7NaEp/5ZlpE720apJ4uSqmRrLwk5Y1eKQvT46mGOk3rC9ZPIMXc8mB10/
mJ9mTubi1t4uIPnBl/T1T7f8QhNtr9hOY6wjLf1LoMeJ1XVNBqA+2uydOlBJ1iop
RQ7y/Jl1SZ/gBzKCmvjPHT2+0Oui9oXGd9bQi0xQKO5Lus/nAIg=
=Wdw1
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.3 kernel cycle:
Core changes:
- Device links can optionally be added between a pin control producer
and its consumers. This will affect how the system power management
is handled: a pin controller will not suspend before all of its
consumers have been suspended.
This was necessary for the ST Microelectronics STMFX expander and
need to be tested on other systems as well: it makes sense to make
this default in the long run.
Right now it is opt-in per driver.
- Drive strength can be specified in microamps. With decreases in
silicon technology, milliamps isn't granular enough, let's make it
possible to select drive strengths in microamps.
Right now the Meson (AMlogic) driver needs this.
New drivers:
- New subdriver for the Tegra 194 SoC.
- New subdriver for the Qualcomm SDM845.
- New subdriver for the Qualcomm SM8150.
- New subdriver for the Freescale i.MX8MN (Freescale is now a product
line of NXP).
- New subdriver for Marvell MV98DX1135.
Driver improvements:
- The Bitmain BM1880 driver now supports pin config in addition to
muxing.
- The Qualcomm drivers can now reserve some GPIOs as taken aside and
not usable for users. This is used in ACPI systems to take out some
GPIO lines used by the BIOS so that noone else (neither kernel nor
userspace) will play with them by mistake and crash the machine.
- A slew of refurbishing around the Aspeed drivers (board management
controllers for servers) in preparation for the new Aspeed AST2600
SoC.
- A slew of improvements over the SH PFC drivers as usual.
- Misc cleanups and fixes"
* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
pinctrl: aspeed: Strip moved macros and structs from private header
pinctrl: aspeed: Fix missed include
pinctrl: baytrail: Use GENMASK() consistently
pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
pinctrl: qcom: Add SM8150 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
dt-bindings: pinctrl: qcom: Document missing gpio nodes
pinctrl: aspeed: Add implementation-related documentation
pinctrl: aspeed: Split out pinmux from general pinctrl
pinctrl: aspeed: Clarify comment about strapping W1C
pinctrl: aspeed: Correct comment that is no longer true
MAINTAINERS: Add entry for ASPEED pinctrl drivers
dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
dt-bindings: pinctrl: aspeed: Split bindings document in two
pinctrl: qcom: Add irq_enable callback for msm gpio
pinctrl: madera: Fixup SPDX headers
pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
pinctrl: tegra: Add bitmask support for parked bits
...
137 lines
4.4 KiB
Plaintext
137 lines
4.4 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# Broadcom pinctrl drivers
|
|
#
|
|
|
|
config PINCTRL_BCM281XX
|
|
bool "Broadcom BCM281xx pinctrl driver"
|
|
depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
select REGMAP_MMIO
|
|
default ARCH_BCM_MOBILE
|
|
help
|
|
Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
|
|
for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
|
|
BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
|
|
framework. GPIO is provided by a separate GPIO driver.
|
|
|
|
config PINCTRL_BCM2835
|
|
bool "Broadcom BCM2835 GPIO (with PINCONF) driver"
|
|
depends on OF && (ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST)
|
|
select PINMUX
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
select GPIOLIB_IRQCHIP
|
|
default ARCH_BCM2835 || ARCH_BRCMSTB
|
|
help
|
|
Say Y here to enable the Broadcom BCM2835 GPIO driver.
|
|
|
|
config PINCTRL_IPROC_GPIO
|
|
bool "Broadcom iProc GPIO (with PINCONF) driver"
|
|
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
|
|
select GPIOLIB_IRQCHIP
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
default ARCH_BCM_IPROC
|
|
help
|
|
Say yes here to enable the Broadcom iProc GPIO driver.
|
|
|
|
The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
|
|
same GPIO Controller IP hence this driver could be used for all.
|
|
|
|
The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
|
|
GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
|
|
the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
|
|
supported by this driver.
|
|
|
|
The Broadcom NSP has two GPIO controllers including the ChipcommonA
|
|
GPIO, the ChipcommonB GPIO. Later controller is supported by this
|
|
driver.
|
|
|
|
The Broadcom NS2 has two GPIO controller including the CRMU GPIO,
|
|
the ChipcommonG GPIO. Both controllers are supported by this driver.
|
|
|
|
The Broadcom Stingray GPIO controllers are supported by this driver.
|
|
|
|
All above SoCs GPIO controllers support basic PINCONF functions such
|
|
as bias pull up, pull down, and drive strength configurations, when
|
|
these pins are muxed to GPIO.
|
|
|
|
It provides the framework where pins from the individual GPIO can be
|
|
individually muxed to GPIO function, through interaction with the
|
|
SoCs IOMUX controller. This features could be used only on SoCs which
|
|
support individual pin muxing.
|
|
|
|
config PINCTRL_CYGNUS_MUX
|
|
bool "Broadcom Cygnus IOMUX driver"
|
|
depends on (ARCH_BCM_CYGNUS || COMPILE_TEST)
|
|
depends on OF
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
default ARCH_BCM_CYGNUS
|
|
help
|
|
Say yes here to enable the Broadcom Cygnus IOMUX driver.
|
|
|
|
The Broadcom Cygnus IOMUX driver supports group based IOMUX
|
|
configuration, with the exception that certain individual pins
|
|
can be overridden to GPIO function
|
|
|
|
config PINCTRL_NS
|
|
bool "Broadcom Northstar pins driver"
|
|
depends on OF && (ARCH_BCM_5301X || COMPILE_TEST)
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
default ARCH_BCM_5301X
|
|
help
|
|
Say yes here to enable the Broadcom NS SoC pins driver.
|
|
|
|
The Broadcom Northstar pins driver supports muxing multi-purpose pins
|
|
that can be used for various functions (e.g. SPI, I2C, UART) as well
|
|
as GPIOs.
|
|
|
|
config PINCTRL_NSP_GPIO
|
|
bool "Broadcom NSP GPIO (with PINCONF) driver"
|
|
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
|
|
select GPIOLIB_IRQCHIP
|
|
select PINCONF
|
|
select GENERIC_PINCONF
|
|
default ARCH_BCM_NSP
|
|
help
|
|
Say yes here to enable the Broadcom NSP GPIO driver.
|
|
|
|
The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
|
|
supported by this driver.
|
|
|
|
The ChipcommonA GPIO controller support basic PINCONF functions such
|
|
as bias pull up, pull down, and drive strength configurations, when
|
|
these pins are muxed to GPIO.
|
|
|
|
config PINCTRL_NS2_MUX
|
|
bool "Broadcom Northstar2 pinmux driver"
|
|
depends on OF
|
|
depends on ARCH_BCM_IPROC || COMPILE_TEST
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
default ARM64 && ARCH_BCM_IPROC
|
|
help
|
|
Say yes here to enable the Broadcom NS2 MUX driver.
|
|
|
|
The Broadcom Northstar2 IOMUX driver supports group based IOMUX
|
|
configuration.
|
|
|
|
config PINCTRL_NSP_MUX
|
|
bool "Broadcom NSP IOMUX driver"
|
|
depends on (ARCH_BCM_NSP || COMPILE_TEST)
|
|
depends on OF
|
|
select PINMUX
|
|
select GENERIC_PINCONF
|
|
default ARCH_BCM_NSP
|
|
help
|
|
Say yes here to enable the Broadcom NSP SOC IOMUX driver.
|
|
|
|
The Broadcom Northstar Plus IOMUX driver supports pin based IOMUX
|
|
configuration, with certain individual pins can be overridden
|
|
to GPIO function.
|