Moshe Lazer 0ba422410b net/mlx5: Fix global UAR mapping ... Avoid double mapping of io mapped memory, Device page may be mapped to non-cached(NC) or to write-combining(WC). The code before this fix tries to map it both to WC and NC contrary to what stated in Intel's software developer manual. Here we remove the global WC mapping of all UARS "dev->priv.bf_mapping", since UAR mapping should be decided per UAR (e.g we want different mappings for EQs, CQs vs QPs). Caller will now have to choose whether to map via write-combining API or not. mlx5e SQs will choose write-combining in order to perform BlueFlame writes. Fixes: 88a85f99e5 ('TX latency optimization to save DMA reads') Signed-off-by: Moshe Lazer <moshel@mellanox.com> Reviewed-by: Achiad Shochat <achiad@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2016-03-01 17:28:00 -05:00
..
cmd.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
cq.h	net/mlx5_core: Fix trimming down IRQ number	2016-01-17 12:08:04 -05:00
device.h	net/mlx5e: Wake On LAN support	2016-02-24 13:50:21 -05:00
doorbell.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
driver.h	net/mlx5: Fix global UAR mapping	2016-03-01 17:28:00 -05:00
fs.h	IB/mlx5: Add flow steering support	2016-01-11 17:48:53 -05:00
mlx5_ifc.h	net/mlx5e: Wake On LAN support	2016-02-24 13:50:21 -05:00
port.h	net/mlx5e: Wake On LAN support	2016-02-24 13:50:21 -05:00
qp.h	{IB, net}/mlx5: Move the modify QP operation table to mlx5_ib	2016-01-21 12:01:09 -05:00
srq.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
transobj.h	IB/mlx5: Support setting Ethernet priority for Raw Packet QPs	2016-01-21 12:01:09 -05:00
vport.h	Initial roundup of 4.5 merge window patches	2016-01-23 18:45:06 -08:00