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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ab66d1fba
Nvlink2 supports address translation services (ATS) allowing devices to request address translations from an mmu known as the nest MMU which is setup to walk the CPU page tables. To access this functionality certain firmware calls are required to setup and manage hardware context tables in the nvlink processing unit (NPU). The NPU also manages forwarding of TLB invalidates (known as address translation shootdowns/ATSDs) to attached devices. This patch exports several methods to allow device drivers to register a process id (PASID/PID) in the hardware tables and to receive notification of when a device should stop issuing address translation requests (ATRs). It also adds a fault handler to allow device drivers to demand fault pages in. Signed-off-by: Alistair Popple <alistair@popple.id.au> [mpe: Fix up comment formatting, use flush_tlb_mm()] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
169 lines
4.7 KiB
C
169 lines
4.7 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
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#define _ASM_POWERPC_BOOK3S_64_MMU_H_
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#ifndef __ASSEMBLY__
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def {
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unsigned int shift; /* number of bits */
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int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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union {
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
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};
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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#endif /* __ASSEMBLY__ */
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/* 64-bit classic hash table MMU */
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#include <asm/book3s/64/mmu-hash.h>
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#ifndef __ASSEMBLY__
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/*
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* ISA 3.0 partition and process table entry format
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*/
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struct prtb_entry {
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__be64 prtb0;
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__be64 prtb1;
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};
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extern struct prtb_entry *process_tb;
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struct patb_entry {
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__be64 patb0;
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__be64 patb1;
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};
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extern struct patb_entry *partition_tb;
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/* Bits in patb0 field */
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#define PATB_HR (1UL << 63)
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#define RPDB_MASK 0x0fffffffffffff00UL
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#define RPDB_SHIFT (1UL << 8)
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#define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
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#define RTS1_MASK (3UL << RTS1_SHIFT)
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#define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
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#define RTS2_MASK (7UL << RTS2_SHIFT)
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#define RPDS_MASK 0x1f /* root page dir. size field */
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/* Bits in patb1 field */
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#define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
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#define PRTS_MASK 0x1f /* process table size field */
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#define PRTB_MASK 0x0ffffffffffff000UL
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/*
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* Limit process table to PAGE_SIZE table. This
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* also limit the max pid we can support.
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* MAX_USER_CONTEXT * 16 bytes of space.
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*/
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#define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
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#define PRTB_ENTRIES (1ul << CONTEXT_BITS)
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/*
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* Power9 currently only support 64K partition table size.
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*/
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#define PATB_SIZE_SHIFT 16
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typedef unsigned long mm_context_id_t;
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struct spinlock;
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/* Maximum possible number of NPUs in a system. */
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#define NV_MAX_NPUS 8
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typedef struct {
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mm_context_id_t id;
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u16 user_psize; /* page size index */
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/* NPU NMMU context */
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struct npu_context *npu_context;
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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unsigned long addr_limit;
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#else
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u16 sllp; /* SLB page size encoding */
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#endif
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unsigned long vdso_base;
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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struct subpage_prot_table spt;
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#endif /* CONFIG_PPC_SUBPAGE_PROT */
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#ifdef CONFIG_PPC_ICSWX
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struct spinlock *cop_lockp; /* guard acop and cop_pid */
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unsigned long acop; /* mask of enabled coprocessor types */
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unsigned int cop_pid; /* pid value used with coprocessors */
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#endif /* CONFIG_PPC_ICSWX */
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#ifdef CONFIG_PPC_64K_PAGES
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/* for 4K PTE fragment support */
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void *pte_frag;
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#endif
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#ifdef CONFIG_SPAPR_TCE_IOMMU
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struct list_head iommu_group_mem_list;
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#endif
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} mm_context_t;
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/*
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* The current system page and segment sizes
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*/
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_vmemmap_psize;
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extern int mmu_io_psize;
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/* MMU initialization */
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void mmu_early_init_devtree(void);
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void hash__early_init_devtree(void);
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void radix__early_init_devtree(void);
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extern void radix_init_native(void);
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extern void hash__early_init_mmu(void);
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extern void radix__early_init_mmu(void);
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static inline void early_init_mmu(void)
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{
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if (radix_enabled())
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return radix__early_init_mmu();
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return hash__early_init_mmu();
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}
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extern void hash__early_init_mmu_secondary(void);
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extern void radix__early_init_mmu_secondary(void);
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static inline void early_init_mmu_secondary(void)
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{
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if (radix_enabled())
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return radix__early_init_mmu_secondary();
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return hash__early_init_mmu_secondary();
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}
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extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size);
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extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size);
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static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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if (early_radix_enabled())
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return radix__setup_initial_memory_limit(first_memblock_base,
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first_memblock_size);
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return hash__setup_initial_memory_limit(first_memblock_base,
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first_memblock_size);
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}
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extern int (*register_process_table)(unsigned long base, unsigned long page_size,
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unsigned long tbl_size);
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#ifdef CONFIG_PPC_PSERIES
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extern void radix_init_pseries(void);
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#else
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static inline void radix_init_pseries(void) { };
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
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