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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
634 lines
18 KiB
C
634 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __OMAP_DRM_DSS_H
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#define __OMAP_DRM_DSS_H
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <video/videomode.h>
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#include <linux/platform_data/omapdss.h>
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#include <uapi/drm/drm_mode.h>
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#include <drm/drm_crtc.h>
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#define DISPC_IRQ_FRAMEDONE (1 << 0)
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#define DISPC_IRQ_VSYNC (1 << 1)
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#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
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#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
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#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
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#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
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#define DISPC_IRQ_GFX_END_WIN (1 << 7)
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#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
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#define DISPC_IRQ_OCP_ERR (1 << 9)
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#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
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#define DISPC_IRQ_VID1_END_WIN (1 << 11)
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#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
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#define DISPC_IRQ_VID2_END_WIN (1 << 13)
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#define DISPC_IRQ_SYNC_LOST (1 << 14)
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#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
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#define DISPC_IRQ_WAKEUP (1 << 16)
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#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
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#define DISPC_IRQ_VSYNC2 (1 << 18)
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#define DISPC_IRQ_VID3_END_WIN (1 << 19)
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#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
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#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
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#define DISPC_IRQ_FRAMEDONETV (1 << 24)
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#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
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#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
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#define DISPC_IRQ_VSYNC3 (1 << 28)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
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#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
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struct dss_device;
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struct omap_drm_private;
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struct omap_dss_device;
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struct dispc_device;
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struct dss_device;
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struct dss_lcd_mgr_config;
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struct snd_aes_iec958;
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struct snd_cea_861_aud_if;
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struct hdmi_avi_infoframe;
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struct drm_connector;
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enum omap_display_type {
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OMAP_DISPLAY_TYPE_NONE = 0,
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OMAP_DISPLAY_TYPE_DPI = 1 << 0,
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OMAP_DISPLAY_TYPE_DBI = 1 << 1,
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OMAP_DISPLAY_TYPE_SDI = 1 << 2,
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OMAP_DISPLAY_TYPE_DSI = 1 << 3,
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OMAP_DISPLAY_TYPE_VENC = 1 << 4,
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OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
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OMAP_DISPLAY_TYPE_DVI = 1 << 6,
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};
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enum omap_plane_id {
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OMAP_DSS_GFX = 0,
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OMAP_DSS_VIDEO1 = 1,
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OMAP_DSS_VIDEO2 = 2,
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OMAP_DSS_VIDEO3 = 3,
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OMAP_DSS_WB = 4,
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};
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enum omap_channel {
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OMAP_DSS_CHANNEL_LCD = 0,
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OMAP_DSS_CHANNEL_DIGIT = 1,
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OMAP_DSS_CHANNEL_LCD2 = 2,
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OMAP_DSS_CHANNEL_LCD3 = 3,
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OMAP_DSS_CHANNEL_WB = 4,
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};
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enum omap_color_mode {
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_UNUSED_,
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};
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enum omap_dss_load_mode {
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OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
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OMAP_DSS_LOAD_CLUT_ONLY = 1,
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OMAP_DSS_LOAD_FRAME_ONLY = 2,
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OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
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};
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enum omap_dss_trans_key_type {
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OMAP_DSS_COLOR_KEY_GFX_DST = 0,
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OMAP_DSS_COLOR_KEY_VID_SRC = 1,
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};
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enum omap_dss_signal_level {
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OMAPDSS_SIG_ACTIVE_LOW,
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OMAPDSS_SIG_ACTIVE_HIGH,
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};
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enum omap_dss_signal_edge {
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OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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OMAPDSS_DRIVE_SIG_RISING_EDGE,
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};
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enum omap_dss_venc_type {
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OMAP_DSS_VENC_TYPE_COMPOSITE,
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OMAP_DSS_VENC_TYPE_SVIDEO,
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};
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enum omap_dss_dsi_pixel_format {
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OMAP_DSS_DSI_FMT_RGB888,
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OMAP_DSS_DSI_FMT_RGB666,
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OMAP_DSS_DSI_FMT_RGB666_PACKED,
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OMAP_DSS_DSI_FMT_RGB565,
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};
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enum omap_dss_dsi_mode {
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OMAP_DSS_DSI_CMD_MODE = 0,
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OMAP_DSS_DSI_VIDEO_MODE,
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};
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enum omap_display_caps {
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OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
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OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
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};
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enum omap_dss_display_state {
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OMAP_DSS_DISPLAY_DISABLED = 0,
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OMAP_DSS_DISPLAY_ACTIVE,
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};
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enum omap_dss_rotation_type {
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OMAP_DSS_ROT_NONE = 0,
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OMAP_DSS_ROT_TILER = 1 << 0,
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};
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enum omap_overlay_caps {
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OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
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OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
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OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
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OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
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OMAP_DSS_OVL_CAP_POS = 1 << 4,
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OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
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};
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enum omap_dss_output_id {
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OMAP_DSS_OUTPUT_DPI = 1 << 0,
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OMAP_DSS_OUTPUT_DBI = 1 << 1,
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OMAP_DSS_OUTPUT_SDI = 1 << 2,
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OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
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OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
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OMAP_DSS_OUTPUT_VENC = 1 << 5,
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OMAP_DSS_OUTPUT_HDMI = 1 << 6,
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};
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/* DSI */
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enum omap_dss_dsi_trans_mode {
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/* Sync Pulses: both sync start and end packets sent */
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OMAP_DSS_DSI_PULSE_MODE,
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/* Sync Events: only sync start packets sent */
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OMAP_DSS_DSI_EVENT_MODE,
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/* Burst: only sync start packets sent, pixels are time compressed */
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OMAP_DSS_DSI_BURST_MODE,
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};
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struct omap_dss_dsi_videomode_timings {
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unsigned long hsclk;
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unsigned int ndl;
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unsigned int bitspp;
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/* pixels */
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u16 hact;
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/* lines */
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u16 vact;
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/* DSI video mode blanking data */
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/* Unit: byte clock cycles */
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u16 hss;
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u16 hsa;
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u16 hse;
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u16 hfp;
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u16 hbp;
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/* Unit: line clocks */
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u16 vsa;
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u16 vfp;
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u16 vbp;
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/* DSI blanking modes */
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int blanking_mode;
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int hsa_blanking_mode;
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int hbp_blanking_mode;
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int hfp_blanking_mode;
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enum omap_dss_dsi_trans_mode trans_mode;
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bool ddr_clk_always_on;
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int window_sync;
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};
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struct omap_dss_dsi_config {
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enum omap_dss_dsi_mode mode;
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enum omap_dss_dsi_pixel_format pixel_format;
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const struct videomode *vm;
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unsigned long hs_clk_min, hs_clk_max;
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unsigned long lp_clk_min, lp_clk_max;
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bool ddr_clk_always_on;
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enum omap_dss_dsi_trans_mode trans_mode;
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};
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struct omap_dss_cpr_coefs {
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s16 rr, rg, rb;
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s16 gr, gg, gb;
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s16 br, bg, bb;
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};
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struct omap_overlay_info {
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dma_addr_t paddr;
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dma_addr_t p_uv_addr; /* for NV12 format */
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u16 screen_width;
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u16 width;
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u16 height;
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u32 fourcc;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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u16 pos_x;
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u16 pos_y;
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u16 out_width; /* if 0, out_width == width */
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u16 out_height; /* if 0, out_height == height */
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u8 global_alpha;
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u8 pre_mult_alpha;
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u8 zorder;
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};
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struct omap_overlay_manager_info {
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u32 default_color;
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enum omap_dss_trans_key_type trans_key_type;
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u32 trans_key;
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bool trans_enabled;
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bool partial_alpha_enabled;
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bool cpr_enable;
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struct omap_dss_cpr_coefs cpr_coefs;
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};
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/* 22 pins means 1 clk lane and 10 data lanes */
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#define OMAP_DSS_MAX_DSI_PINS 22
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struct omap_dsi_pin_config {
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int num_pins;
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/*
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* pin numbers in the following order:
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* clk+, clk-
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* data1+, data1-
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* data2+, data2-
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* ...
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*/
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int pins[OMAP_DSS_MAX_DSI_PINS];
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};
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struct omap_dss_writeback_info {
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u32 paddr;
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u32 p_uv_addr;
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u16 buf_width;
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u16 width;
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u16 height;
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u32 fourcc;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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u8 pre_mult_alpha;
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};
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struct omapdss_hdmi_ops {
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void (*lost_hotplug)(struct omap_dss_device *dssdev);
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int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
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int (*set_infoframe)(struct omap_dss_device *dssdev,
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const struct hdmi_avi_infoframe *avi);
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};
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struct omapdss_dsi_ops {
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void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
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bool enter_ulps);
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/* bus configuration */
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int (*set_config)(struct omap_dss_device *dssdev,
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const struct omap_dss_dsi_config *cfg);
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int (*configure_pins)(struct omap_dss_device *dssdev,
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const struct omap_dsi_pin_config *pin_cfg);
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void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
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bool enable);
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int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
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int (*update)(struct omap_dss_device *dssdev, int channel,
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void (*callback)(int, void *), void *data);
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void (*bus_lock)(struct omap_dss_device *dssdev);
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void (*bus_unlock)(struct omap_dss_device *dssdev);
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int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
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void (*disable_video_output)(struct omap_dss_device *dssdev,
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int channel);
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int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
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int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
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int vc_id);
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void (*release_vc)(struct omap_dss_device *dssdev, int channel);
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/* data transfer */
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int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
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u8 *data, int len);
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int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
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u8 *data, int len);
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int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
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u8 *data, int len);
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int (*gen_write)(struct omap_dss_device *dssdev, int channel,
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u8 *data, int len);
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int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
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u8 *data, int len);
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int (*gen_read)(struct omap_dss_device *dssdev, int channel,
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u8 *reqdata, int reqlen,
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u8 *data, int len);
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int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
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int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
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int channel, u16 plen);
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};
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struct omap_dss_device_ops {
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int (*connect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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void (*disconnect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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void (*pre_enable)(struct omap_dss_device *dssdev);
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void (*enable)(struct omap_dss_device *dssdev);
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void (*disable)(struct omap_dss_device *dssdev);
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void (*post_disable)(struct omap_dss_device *dssdev);
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int (*check_timings)(struct omap_dss_device *dssdev,
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struct drm_display_mode *mode);
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void (*set_timings)(struct omap_dss_device *dssdev,
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const struct drm_display_mode *mode);
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bool (*detect)(struct omap_dss_device *dssdev);
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void (*register_hpd_cb)(struct omap_dss_device *dssdev,
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void (*cb)(void *cb_data,
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enum drm_connector_status status),
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void *cb_data);
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void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
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int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
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int (*get_modes)(struct omap_dss_device *dssdev,
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struct drm_connector *connector);
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union {
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const struct omapdss_hdmi_ops hdmi;
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const struct omapdss_dsi_ops dsi;
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};
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};
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/**
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* enum omap_dss_device_ops_flag - Indicates which device ops are supported
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* @OMAP_DSS_DEVICE_OP_DETECT: The device supports output connection detection
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* @OMAP_DSS_DEVICE_OP_HPD: The device supports all hot-plug-related operations
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* @OMAP_DSS_DEVICE_OP_EDID: The device supports reading EDID
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* @OMAP_DSS_DEVICE_OP_MODES: The device supports reading modes
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*/
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enum omap_dss_device_ops_flag {
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OMAP_DSS_DEVICE_OP_DETECT = BIT(0),
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OMAP_DSS_DEVICE_OP_HPD = BIT(1),
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OMAP_DSS_DEVICE_OP_EDID = BIT(2),
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OMAP_DSS_DEVICE_OP_MODES = BIT(3),
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};
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struct omap_dss_device {
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struct device *dev;
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struct module *owner;
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struct dss_device *dss;
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struct omap_dss_device *next;
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struct drm_bridge *bridge;
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struct drm_panel *panel;
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struct list_head list;
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/*
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* DSS type that this device generates (for DSS internal devices) or
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* requires (for external encoders, connectors and panels). Must be a
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* non-zero (different than OMAP_DISPLAY_TYPE_NONE) value.
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*/
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enum omap_display_type type;
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/*
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* True if the device is a display (panel or connector) at the end of
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* the pipeline, false otherwise.
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*/
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bool display;
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const char *name;
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const struct omap_dss_driver *driver;
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const struct omap_dss_device_ops *ops;
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unsigned long ops_flags;
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u32 bus_flags;
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enum omap_display_caps caps;
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enum omap_dss_display_state state;
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/* OMAP DSS output specific fields */
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/* DISPC channel for this output */
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enum omap_channel dispc_channel;
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/* output instance */
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enum omap_dss_output_id id;
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/* bitmask of port numbers in DT */
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unsigned int of_ports;
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};
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struct omap_dss_driver {
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int (*update)(struct omap_dss_device *dssdev,
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u16 x, u16 y, u16 w, u16 h);
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int (*sync)(struct omap_dss_device *dssdev);
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int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
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int (*get_te)(struct omap_dss_device *dssdev);
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int (*memory_read)(struct omap_dss_device *dssdev,
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void *buf, size_t size,
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u16 x, u16 y, u16 w, u16 h);
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};
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struct dss_device *omapdss_get_dss(void);
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void omapdss_set_dss(struct dss_device *dss);
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static inline bool omapdss_is_initialized(void)
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{
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return !!omapdss_get_dss();
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}
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void omapdss_display_init(struct omap_dss_device *dssdev);
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struct omap_dss_device *omapdss_display_get(struct omap_dss_device *output);
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int omapdss_display_get_modes(struct drm_connector *connector,
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const struct videomode *vm);
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void omapdss_device_register(struct omap_dss_device *dssdev);
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void omapdss_device_unregister(struct omap_dss_device *dssdev);
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struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
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void omapdss_device_put(struct omap_dss_device *dssdev);
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struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
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int omapdss_device_connect(struct dss_device *dss,
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struct omap_dss_device *src,
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struct omap_dss_device *dst);
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void omapdss_device_disconnect(struct omap_dss_device *src,
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struct omap_dss_device *dst);
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void omapdss_device_pre_enable(struct omap_dss_device *dssdev);
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void omapdss_device_enable(struct omap_dss_device *dssdev);
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void omapdss_device_disable(struct omap_dss_device *dssdev);
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void omapdss_device_post_disable(struct omap_dss_device *dssdev);
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int omap_dss_get_num_overlay_managers(void);
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int omap_dss_get_num_overlays(void);
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#define for_each_dss_output(d) \
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while ((d = omapdss_device_next_output(d)) != NULL)
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struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
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int omapdss_device_init_output(struct omap_dss_device *out);
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void omapdss_device_cleanup_output(struct omap_dss_device *out);
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typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
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int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
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int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
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int omapdss_compat_init(void);
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void omapdss_compat_uninit(void);
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static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
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{
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return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
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}
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struct omap_dss_device *
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omapdss_of_find_connected_device(struct device_node *node, unsigned int port);
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enum dss_writeback_channel {
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DSS_WB_LCD1_MGR = 0,
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DSS_WB_LCD2_MGR = 1,
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DSS_WB_TV_MGR = 2,
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DSS_WB_OVL0 = 3,
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DSS_WB_OVL1 = 4,
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DSS_WB_OVL2 = 5,
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DSS_WB_OVL3 = 6,
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DSS_WB_LCD3_MGR = 7,
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};
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struct dss_mgr_ops {
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void (*start_update)(struct omap_drm_private *priv,
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enum omap_channel channel);
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int (*enable)(struct omap_drm_private *priv,
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enum omap_channel channel);
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void (*disable)(struct omap_drm_private *priv,
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enum omap_channel channel);
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void (*set_timings)(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct videomode *vm);
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void (*set_lcd_config)(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct dss_lcd_mgr_config *config);
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int (*register_framedone_handler)(struct omap_drm_private *priv,
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enum omap_channel channel,
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void (*handler)(void *), void *data);
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void (*unregister_framedone_handler)(struct omap_drm_private *priv,
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enum omap_channel channel,
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void (*handler)(void *), void *data);
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};
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int dss_install_mgr_ops(struct dss_device *dss,
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const struct dss_mgr_ops *mgr_ops,
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struct omap_drm_private *priv);
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void dss_uninstall_mgr_ops(struct dss_device *dss);
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void dss_mgr_set_timings(struct omap_dss_device *dssdev,
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const struct videomode *vm);
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void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
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const struct dss_lcd_mgr_config *config);
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int dss_mgr_enable(struct omap_dss_device *dssdev);
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void dss_mgr_disable(struct omap_dss_device *dssdev);
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void dss_mgr_start_update(struct omap_dss_device *dssdev);
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int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
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void (*handler)(void *), void *data);
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void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
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void (*handler)(void *), void *data);
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|
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/* dispc ops */
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|
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struct dispc_ops {
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u32 (*read_irqstatus)(struct dispc_device *dispc);
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void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
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void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
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|
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int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
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|
void *dev_id);
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void (*free_irq)(struct dispc_device *dispc, void *dev_id);
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|
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|
int (*runtime_get)(struct dispc_device *dispc);
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|
void (*runtime_put)(struct dispc_device *dispc);
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|
|
|
int (*get_num_ovls)(struct dispc_device *dispc);
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|
int (*get_num_mgrs)(struct dispc_device *dispc);
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|
|
|
u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc);
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|
|
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void (*mgr_enable)(struct dispc_device *dispc,
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enum omap_channel channel, bool enable);
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|
bool (*mgr_is_enabled)(struct dispc_device *dispc,
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|
enum omap_channel channel);
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|
u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc,
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|
enum omap_channel channel);
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|
u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc,
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|
enum omap_channel channel);
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|
u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc,
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|
enum omap_channel channel);
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|
bool (*mgr_go_busy)(struct dispc_device *dispc,
|
|
enum omap_channel channel);
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|
void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel);
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|
void (*mgr_set_lcd_config)(struct dispc_device *dispc,
|
|
enum omap_channel channel,
|
|
const struct dss_lcd_mgr_config *config);
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|
int (*mgr_check_timings)(struct dispc_device *dispc,
|
|
enum omap_channel channel,
|
|
const struct videomode *vm);
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|
void (*mgr_set_timings)(struct dispc_device *dispc,
|
|
enum omap_channel channel,
|
|
const struct videomode *vm);
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|
void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel,
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|
const struct omap_overlay_manager_info *info);
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|
u32 (*mgr_gamma_size)(struct dispc_device *dispc,
|
|
enum omap_channel channel);
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|
void (*mgr_set_gamma)(struct dispc_device *dispc,
|
|
enum omap_channel channel,
|
|
const struct drm_color_lut *lut,
|
|
unsigned int length);
|
|
|
|
int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane,
|
|
bool enable);
|
|
int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane,
|
|
const struct omap_overlay_info *oi,
|
|
const struct videomode *vm, bool mem_to_mem,
|
|
enum omap_channel channel);
|
|
|
|
const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc,
|
|
enum omap_plane_id plane);
|
|
|
|
u32 (*wb_get_framedone_irq)(struct dispc_device *dispc);
|
|
int (*wb_setup)(struct dispc_device *dispc,
|
|
const struct omap_dss_writeback_info *wi,
|
|
bool mem_to_mem, const struct videomode *vm,
|
|
enum dss_writeback_channel channel_in);
|
|
bool (*has_writeback)(struct dispc_device *dispc);
|
|
bool (*wb_go_busy)(struct dispc_device *dispc);
|
|
void (*wb_go)(struct dispc_device *dispc);
|
|
};
|
|
|
|
struct dispc_device *dispc_get_dispc(struct dss_device *dss);
|
|
const struct dispc_ops *dispc_get_ops(struct dss_device *dss);
|
|
|
|
bool omapdss_stack_is_ready(void);
|
|
void omapdss_gather_components(struct device *dev);
|
|
|
|
#endif /* __OMAP_DRM_DSS_H */
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