mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 12:46:41 +07:00
684a586741
This adds support for the TQ TQMa7D SoM together with the MBa7 carrier board and it's based on the NXP i.MX7Dual SoC. Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
120 lines
3.0 KiB
Plaintext
120 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR X11
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/*
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* Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
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*
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* Copyright (C) 2016 TQ Systems GmbH
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* Author: Markus Niebel <Markus.Niebel@tq-group.com>
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* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
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*/
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/dts-v1/;
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#include "imx7d-tqma7.dtsi"
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#include "imx7-mba7.dtsi"
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/ {
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model = "TQ Systems TQMa7D board on MBa7 carrier board";
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compatible = "tq,imx7d-mba7", "fsl,imx7d";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-delay = <1>;
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phy-supply = <®_fec2_pwdn>;
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phy-handle = <ðphy2_0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy2_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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/* LED1: Link/Activity, LED2: error */
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ti,led-function = <0x0db0>;
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/* active low, LED1/2 driven by phy */
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ti,led-ctrl = <0x1001>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_mba7_1>;
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
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MX7D_PAD_SD2_WP__ENET2_MDC 0x00
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MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
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MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
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MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
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MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
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MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
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MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
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MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
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MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
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MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
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MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
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MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
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MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
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/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
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MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
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/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
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MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
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>;
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};
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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/* #pcie_wake */
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MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
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/* #pcie_rst */
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MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
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/* #pcie_dis */
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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_usbotg2: usbotg2grp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
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MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
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>;
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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/* 1.5V logically from 3.3V */
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/* probe deferral not supported */
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/* pcie-bus-supply = <®_mpcie_1v5>; */
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reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
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disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
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power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&usbotg2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg2>;
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vbus-supply = <®_usb_otg2_vbus>;
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srp-disable;
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hnp-disable;
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adp-disable;
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dr_mode = "host";
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status = "okay";
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};
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