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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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187e5cd2d1
Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
129 lines
2.7 KiB
C
129 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum gate clock driver
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "gate.h"
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static void clk_gate_toggle(const struct sprd_gate *sg, bool en)
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{
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const struct sprd_clk_common *common = &sg->common;
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unsigned int reg;
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bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? true : false;
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set ^= en;
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regmap_read(common->regmap, common->reg, ®);
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if (set)
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reg |= sg->enable_mask;
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else
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reg &= ~sg->enable_mask;
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regmap_write(common->regmap, common->reg, reg);
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}
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static void clk_sc_gate_toggle(const struct sprd_gate *sg, bool en)
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{
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const struct sprd_clk_common *common = &sg->common;
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bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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unsigned int offset;
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set ^= en;
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/*
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* Each set/clear gate clock has three registers:
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* common->reg - base register
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* common->reg + offset - set register
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* common->reg + 2 * offset - clear register
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*/
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offset = set ? sg->sc_offset : sg->sc_offset * 2;
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regmap_write(common->regmap, common->reg + offset,
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sg->enable_mask);
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}
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static void sprd_gate_disable(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_gate_toggle(sg, false);
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}
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static int sprd_gate_enable(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_gate_toggle(sg, true);
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return 0;
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}
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static void sprd_sc_gate_disable(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_sc_gate_toggle(sg, false);
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}
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static int sprd_sc_gate_enable(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_sc_gate_toggle(sg, true);
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return 0;
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}
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static int sprd_pll_sc_gate_prepare(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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clk_sc_gate_toggle(sg, true);
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udelay(sg->udelay);
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return 0;
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}
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static int sprd_gate_is_enabled(struct clk_hw *hw)
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{
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struct sprd_gate *sg = hw_to_sprd_gate(hw);
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struct sprd_clk_common *common = &sg->common;
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unsigned int reg;
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regmap_read(common->regmap, common->reg, ®);
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if (sg->flags & CLK_GATE_SET_TO_DISABLE)
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reg ^= sg->enable_mask;
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reg &= sg->enable_mask;
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return reg ? 1 : 0;
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}
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const struct clk_ops sprd_gate_ops = {
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.disable = sprd_gate_disable,
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.enable = sprd_gate_enable,
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.is_enabled = sprd_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(sprd_gate_ops);
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const struct clk_ops sprd_sc_gate_ops = {
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.disable = sprd_sc_gate_disable,
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.enable = sprd_sc_gate_enable,
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.is_enabled = sprd_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
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const struct clk_ops sprd_pll_sc_gate_ops = {
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.unprepare = sprd_sc_gate_disable,
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.prepare = sprd_pll_sc_gate_prepare,
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.is_enabled = sprd_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
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