mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 05:08:41 +07:00
d4db4e5532
There are three SoC families newly dded to the 32-bit and
64-bit Arm architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012. For
now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl8j31MACgkQmmx57+YA
GNnS7Q//achCOtBeIblV8Fyfp/lTYNpT9hFTQ5cGaoyjl9Lm1rcVCISCEGqIEJAV
FRQBz3YcQWA9pIWIf79oh6QphcoW/wUTCE+cjnHP+EOkqvw9aGFBm4nOUt4Gz92a
+gGs9HqcrxB+3ysQEDGugwRrE6htrOoCnWyurh5zZNvAEry+MV6LBwfxSUrLKy8b
iwnwl/KvWI47mWAj5nJ7fbXAgxRjFdEz+mvNBjqKhJ/OELsnWRXcxmJxF651DEb6
e/ydD7OtrWI1+81/yQxS7SeDlatFHE0JvP4WZHBGm6TB7Z3pdqIZI598UN0lVvbR
jvtljiAa2UA7h6NjscD6ECWktrF8LO8i/8ref7Fr3za/FKiLTYP2BQymnlk5nLAj
RuCvR8oriqBbseZlkGrs4afjpfwurUKNhhjVse/M3ORYYK++Bra6GZWL4gnlA2wB
GbFZ6MAw2bnbKrO6rRTu+F1NFq5/l71LP1r3Li3xbyfZ7I/XJ5aiE6knQ+vtk6Np
pfvCYSILOSnulYZvdaL/W4HV98mzjHSE4eUegGDTMKNv2dVNRGI3Mnnur7+kSXLu
550qg+GXv8JkQlkFkT2BsuaiPULOUKHFtK42fo2XhQL/zoaFlBU7HehtSBdtcKPy
XIlEEk32q+QyABKav2QJnGJMcWzfq2SSmsUliVU72zD38dG/0Fw=
=Yy3D
-----END PGP SIGNATURE-----
Merge tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new ARM SoC support from Arnd Bergmann:
"There are three SoC families newly dded to the 32-bit and 64-bit Arm
architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012.
For now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores"
* tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
ARM: mstar: Correct the compatible string for pmsleep
dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep
dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep
ARM: mstar: Add reboot support
ARM: mstar: Add "pmsleep" node to base dtsi
ARM: mstar: Add PMU
ARM: mstar: Adjust IMI size for infinity3
ARM: mstar: Adjust IMI size for mercury5
ARM: mstar: Adjust IMI size of infinity
ARM: mstar: Add IMI SRAM region
dt-bindings: arm: mstar: Move existing MStar binding descriptions
dt-bindings: arm: mstar: Add binding details for mstar, pmsleep
ARM: mstar: Fix dts filename for 70mai midrive d08
ARM: mstar: Add dts for 70mai midrive d08
ARM: mstar: Add dts for msc313(e) based BreadBee boards
ARM: mstar: Add mercury5 series dtsis
ARM: mstar: Add infinity/infinity3 family dtsis
ARM: mstar: Add Armv7 base dtsi
ARM: mstar: Add binding details for mstar,l3bridge
ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
...
323 lines
7.5 KiB
Plaintext
323 lines
7.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Platform selection"
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config ARCH_ACTIONS
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bool "Actions Semi Platforms"
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select OWL_TIMER
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select PINCTRL
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_AGILEX
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bool "Intel's Agilex SoCFPGA Family"
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help
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This enables support for Intel's Agilex SoCFPGA Family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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config ARCH_ALPINE
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bool "Annapurna Labs Alpine platform"
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select ALPINE_MSI if PCI
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help
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This enables support for the Annapurna Labs Alpine
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Soc family.
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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select TIMER_OF
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select GPIOLIB
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select MFD_CORE
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select PINCTRL
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select PINCTRL_BCM2835
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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help
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This enables support for the Broadcom BCM2837 and BCM2711 SoC.
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These SoCs are used in the Raspberry Pi 3 and 4 devices.
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select DW_APB_ICTL
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_BITMAIN
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bool "Bitmain SoC Platforms"
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help
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This enables support for the Bitmain SoC Family.
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config ARCH_BRCMSTB
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bool "Broadcom Set-Top-Box SoCs"
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select ARCH_HAS_RESET_CONTROLLER
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select BCM7038_L1_IRQ
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select BRCMSTB_L2_IRQ
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select GENERIC_IRQ_CHIP
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select PINCTRL
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help
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This enables support for Broadcom's ARMv8 Set Top Box SoCs
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config ARCH_EXYNOS
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bool "ARMv8 based Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select EXYNOS_CHIPID
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select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
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select EXYNOS_PMU
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select SOC_SAMSUNG
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help
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_SPARX5
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bool "ARMv8 based Microchip Sparx5 SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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help
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This enables support for the Microchip Sparx5 ARMv8-based
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SoC family of TSN-capable gigabit switches.
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The SparX-5 Ethernet switch family provides a rich set of
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switching features such as advanced TCAM-based VLAN and QoS
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processing enabling delivery of differentiated services, and
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security through TCAM-based frame processing using versatile
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content aware processor (VCAP).
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config ARCH_K3
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bool "Texas Instruments Inc. K3 multicore SoC architecture"
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select PM_GENERIC_DOMAINS if PM
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select MAILBOX
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select SOC_TI
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select TI_MESSAGE_MANAGER
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select TI_SCI_PROTOCOL
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select TI_SCI_INTR_IRQCHIP
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select TI_SCI_INTA_IRQCHIP
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select TI_K3_SOCINFO
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help
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This enables support for Texas Instruments' K3 multicore SoC
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architecture.
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config ARCH_LAYERSCAPE
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bool "ARMv8 based Freescale Layerscape SoC family"
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select EDAC_SUPPORT
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help
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This enables support for the Freescale Layerscape SoC family.
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config ARCH_LG1K
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bool "LG Electronics LG1K SoC Family"
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help
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This enables support for LG Electronics LG1K SoC Family
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config ARCH_HISI
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bool "Hisilicon SoC Family"
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select ARM_TIMER_SP804
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select HISILICON_IRQ_MBIGEN if PCI
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select PINCTRL
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help
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This enables support for Hisilicon ARMv8 SoC family
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config ARCH_KEEMBAY
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bool "Keem Bay SoC"
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help
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This enables support for Intel Movidius SoC code-named Keem Bay.
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config ARCH_MEDIATEK
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bool "MediaTek SoC Family"
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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help
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This enables support for MediaTek MT27xx, MT65xx, MT76xx
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& MT81xx ARMv8 SoCs
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config ARCH_MESON
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bool "Amlogic Platforms"
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select PINCTRL
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select PINCTRL_MESON
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select COMMON_CLK_GXBB
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select COMMON_CLK_AXG
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select COMMON_CLK_G12A
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select MESON_IRQ_GPIO
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help
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This enables support for the arm64 based Amlogic SoCs
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such as the s905, S905X/D, S912, A113X/D or S905X/D2
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config ARCH_MVEBU
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bool "Marvell EBU SoC Family"
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select ARMADA_AP806_SYSCON
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select ARMADA_CP110_SYSCON
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select ARMADA_37XX_CLK
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select MVEBU_GICP
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select MVEBU_ICU
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select MVEBU_ODMI
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select MVEBU_PIC
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select MVEBU_SEI
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select OF_GPIO
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select PINCTRL
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select PINCTRL_ARMADA_37XX
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select PINCTRL_ARMADA_AP806
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select PINCTRL_ARMADA_CP110
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help
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This enables support for Marvell EBU familly, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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config ARCH_MXC
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bool "ARMv8 based NXP i.MX SoC family"
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select ARM64_ERRATUM_843419
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select ARM64_ERRATUM_845719 if COMPAT
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select IMX_GPCV2
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select IMX_GPCV2_PM_DOMAINS
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select PM
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select PM_GENERIC_DOMAINS
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select SOC_BUS
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select TIMER_IMX_SYS_CTR
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help
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This enables support for the ARMv8 based SoCs in the
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NXP i.MX family.
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select GPIOLIB
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select PINCTRL
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_REALTEK
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bool "Realtek Platforms"
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Realtek chipsets,
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like the RTD1295.
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select GPIOLIB
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select PINCTRL
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select SOC_BUS
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_ROCKCHIP
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bool "Rockchip Platforms"
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select ARCH_HAS_RESET_CONTROLLER
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select GPIOLIB
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select PINCTRL
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select PINCTRL_ROCKCHIP
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select PM
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select ROCKCHIP_TIMER
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help
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This enables support for the ARMv8 based Rockchip chipsets,
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like the RK3368.
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config ARCH_S32
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bool "NXP S32 SoC Family"
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help
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This enables support for the NXP S32 family of processors.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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This enables support for Altera's Stratix 10 SoCFPGA Family.
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC_PM
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select CLKSRC_MMIO
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select TIMER_OF
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select GENERIC_CLOCKEVENTS
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select GPIOLIB
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_THUNDER2
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bool "Cavium ThunderX2 Server Processors"
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select GPIOLIB
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help
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This enables support for Cavium's ThunderX2 CN99XX family of
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server processors.
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Socionext UniPhier SoC family.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select GPIOLIB
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select PM
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select PM_GENERIC_DOMAINS
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VULCAN
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def_bool n
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZX
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bool "ZTE ZX SoC Family"
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select PINCTRL
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help
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This enables support for ZTE ZX SoC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu
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