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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
280 lines
6.5 KiB
C
280 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define ZX_PWM_MODE 0x0
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#define ZX_PWM_CLKDIV_SHIFT 2
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#define ZX_PWM_CLKDIV_MASK GENMASK(11, 2)
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#define ZX_PWM_CLKDIV(x) (((x) << ZX_PWM_CLKDIV_SHIFT) & \
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ZX_PWM_CLKDIV_MASK)
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#define ZX_PWM_POLAR BIT(1)
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#define ZX_PWM_EN BIT(0)
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#define ZX_PWM_PERIOD 0x4
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#define ZX_PWM_DUTY 0x8
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#define ZX_PWM_CLKDIV_MAX 1023
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#define ZX_PWM_PERIOD_MAX 65535
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struct zx_pwm_chip {
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struct pwm_chip chip;
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struct clk *pclk;
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struct clk *wclk;
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void __iomem *base;
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};
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static inline struct zx_pwm_chip *to_zx_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct zx_pwm_chip, chip);
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}
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static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm,
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unsigned int offset)
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{
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return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);
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}
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static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm,
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unsigned int offset, u32 value)
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{
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writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);
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}
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static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm,
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unsigned int offset, u32 mask, u32 value)
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{
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u32 data;
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data = zx_pwm_readl(zpc, hwpwm, offset);
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data &= ~mask;
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data |= value & mask;
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zx_pwm_writel(zpc, hwpwm, offset, data);
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}
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static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
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unsigned long rate;
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unsigned int div;
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u32 value;
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u64 tmp;
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value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);
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if (value & ZX_PWM_POLAR)
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state->polarity = PWM_POLARITY_NORMAL;
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else
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state->polarity = PWM_POLARITY_INVERSED;
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if (value & ZX_PWM_EN)
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state->enabled = true;
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else
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state->enabled = false;
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div = (value & ZX_PWM_CLKDIV_MASK) >> ZX_PWM_CLKDIV_SHIFT;
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rate = clk_get_rate(zpc->wclk);
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tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);
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tmp *= div * NSEC_PER_SEC;
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);
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tmp *= div * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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}
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static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned int duty_ns, unsigned int period_ns)
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{
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struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
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unsigned int period_cycles, duty_cycles;
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unsigned long long c;
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unsigned int div = 1;
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unsigned long rate;
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/* Find out the best divider */
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rate = clk_get_rate(zpc->wclk);
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while (1) {
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c = rate / div;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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if (c < ZX_PWM_PERIOD_MAX)
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break;
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div++;
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if (div > ZX_PWM_CLKDIV_MAX)
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return -ERANGE;
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}
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/* Calculate duty cycles */
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period_cycles = c;
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c *= duty_ns;
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do_div(c, period_ns);
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duty_cycles = c;
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/*
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* If the PWM is being enabled, we have to temporarily disable it
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* before configuring the registers.
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*/
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if (pwm_is_enabled(pwm))
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);
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/* Set up registers */
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,
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ZX_PWM_CLKDIV(div));
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zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);
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zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);
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/* Re-enable the PWM if needed */
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if (pwm_is_enabled(pwm))
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
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ZX_PWM_EN, ZX_PWM_EN);
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return 0;
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}
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static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
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struct pwm_state cstate;
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int ret;
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pwm_get_state(pwm, &cstate);
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if (state->polarity != cstate.polarity)
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,
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(state->polarity == PWM_POLARITY_INVERSED) ?
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0 : ZX_PWM_POLAR);
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if (state->period != cstate.period ||
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state->duty_cycle != cstate.duty_cycle) {
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ret = zx_pwm_config(chip, pwm, state->duty_cycle,
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state->period);
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if (ret)
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return ret;
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}
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if (state->enabled != cstate.enabled) {
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if (state->enabled) {
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ret = clk_prepare_enable(zpc->wclk);
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if (ret)
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return ret;
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
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ZX_PWM_EN, ZX_PWM_EN);
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} else {
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zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
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ZX_PWM_EN, 0);
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clk_disable_unprepare(zpc->wclk);
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}
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}
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return 0;
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}
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static const struct pwm_ops zx_pwm_ops = {
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.apply = zx_pwm_apply,
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.get_state = zx_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static int zx_pwm_probe(struct platform_device *pdev)
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{
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struct zx_pwm_chip *zpc;
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struct resource *res;
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unsigned int i;
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int ret;
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zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL);
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if (!zpc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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zpc->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(zpc->base))
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return PTR_ERR(zpc->base);
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zpc->pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(zpc->pclk))
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return PTR_ERR(zpc->pclk);
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zpc->wclk = devm_clk_get(&pdev->dev, "wclk");
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if (IS_ERR(zpc->wclk))
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return PTR_ERR(zpc->wclk);
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ret = clk_prepare_enable(zpc->pclk);
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if (ret)
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return ret;
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zpc->chip.dev = &pdev->dev;
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zpc->chip.ops = &zx_pwm_ops;
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zpc->chip.base = -1;
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zpc->chip.npwm = 4;
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zpc->chip.of_xlate = of_pwm_xlate_with_flags;
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zpc->chip.of_pwm_n_cells = 3;
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/*
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* PWM devices may be enabled by firmware, and let's disable all of
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* them initially to save power.
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*/
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for (i = 0; i < zpc->chip.npwm; i++)
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zx_pwm_set_mask(zpc, i, ZX_PWM_MODE, ZX_PWM_EN, 0);
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ret = pwmchip_add(&zpc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, zpc);
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return 0;
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}
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static int zx_pwm_remove(struct platform_device *pdev)
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{
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struct zx_pwm_chip *zpc = platform_get_drvdata(pdev);
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int ret;
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ret = pwmchip_remove(&zpc->chip);
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clk_disable_unprepare(zpc->pclk);
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return ret;
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}
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static const struct of_device_id zx_pwm_dt_ids[] = {
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{ .compatible = "zte,zx296718-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids);
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static struct platform_driver zx_pwm_driver = {
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.driver = {
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.name = "zx-pwm",
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.of_match_table = zx_pwm_dt_ids,
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},
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.probe = zx_pwm_probe,
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.remove = zx_pwm_remove,
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};
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module_platform_driver(zx_pwm_driver);
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MODULE_ALIAS("platform:zx-pwm");
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MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
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MODULE_DESCRIPTION("ZTE ZX PWM Driver");
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MODULE_LICENSE("GPL v2");
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