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-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAl0siFoUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vzi9A//S4jRyyZrgUr88Az0GbgMhE4b3yqc uL7om/Sf+443gG6C+aKkZSM/IE9hrbyIKuYq7GGxDkzZ/HkucZo2yIuAHkPgG4ik QQYJ8fJsmMq1bUht87c1ZZwGP0++Deq/Ns2+VNy/WBYqKLulnV0DvEEaJgPs9C5D ppwccGdo6UghiujBTpE4ddUBjFjjURWqT6wSnMRDQ4EGwfUhG0MWwwHKI4hbBuaL N6refuggdYyUUX5FeUOHa6VF6uTnSSAQ75k+40n4nljdayqoumHLskst77o9q5ZI oXjdpwgmuEqYhfp03HEA4Xo/bBxiRj76NuTiEMKvPokxjpanwbLrdV0GhF0OIlM0 rp1NOI1w+vppFrU+rc2gtq+7hYXFmvdhjS29hFLeD91PP36N5d29jW5NVFpm7GCm n4TMGAOsu8RB+bNua6ZbZVcDk2EnPgQeIcM0ZPoBtPK19Fg/rScdEU4u/aFE1Y0Q C+Ks7D1qCvFpHzl/xAg0oo9v/jFsWef3qnQWOzot964Zz4W4NSVvB9Ox6Vbfj6C4 v331LJmlPxG8fxBNA3q28FrTxcG1NW6sgo3WY9VoSp/vc0aqaPKhm7sbraTt5IrI TwqA/WhnAHv90MQCGFcofANyYTkjPkKk2QBFK6b0suoAmVdwVWWELi1WaZ+HdvgQ JP7YpmC2cXcQBPk= =ZGxL -----END PGP SIGNATURE----- Merge tag 'pci-v5.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration changes: - Evaluate PCI Boot Configuration _DSM to learn if firmware wants us to preserve its resource assignments (Benjamin Herrenschmidt) - Simplify resource distribution (Nicholas Johnson) - Decode 32 GT/s link speed (Gustavo Pimentel) Virtualization: - Fix incorrect caching of VF config space size (Alex Williamson) - Fix VF driver probing sysfs knobs (Alex Williamson) Peer-to-peer DMA: - Fix dma_virt_ops check (Logan Gunthorpe) Altera host bridge driver: - Allow building as module (Ley Foon Tan) Armada 8K host bridge driver: - add PHYs support (Miquel Raynal) DesignWare host bridge driver: - Export APIs to support removable loadable module (Vidya Sagar) - Enable Relaxed Ordering erratum workaround only on Tegra20 & Tegra30 (Vidya Sagar) Hyper-V host bridge driver: - Fix use-after-free in eject (Dexuan Cui) Mobiveil host bridge driver: - Clean up and fix many issues, including non-identify mapped windows, 64-bit windows, multi-MSI, class code, INTx clearing (Hou Zhiqiang) Qualcomm host bridge driver: - Use clk bulk API for 2.4.0 controllers (Bjorn Andersson) - Add QCS404 support (Bjorn Andersson) - Assert PERST for at least 100ms (Niklas Cassel) R-Car host bridge driver: - Add r8a774a1 DT support (Biju Das) Tegra host bridge driver: - Add support for Gen2, opportunistic UpdateFC and ACK (PCIe protocol details) AER, GPIO-based PERST# (Manikanta Maddireddy) - Fix many issues, including power-on failure cases, interrupt masking in suspend, UPHY settings, AFI dynamic clock gating, pending DLL transactions (Manikanta Maddireddy) Xilinx host bridge driver: - Fix NWL Multi-MSI programming (Bharat Kumar Gogada) Endpoint support: - Fix 64bit BAR support (Alan Mikhak) - Fix pcitest build issues (Alan Mikhak, Andy Shevchenko) Bug fixes: - Fix NVIDIA GPU multi-function power dependencies (Abhishek Sahu) - Fix NVIDIA GPU HDA enablement issue (Lukas Wunner) - Ignore lockdep for sysfs "remove" (Marek Vasut) Misc: - Convert docs to reST (Changbin Du, Mauro Carvalho Chehab)" * tag 'pci-v5.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (107 commits) PCI: Enable NVIDIA HDA controllers tools: PCI: Fix installation when `make tools/pci_install` PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: Fix typos and whitespace errors PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr() PCI: mobiveil: Fix infinite-loop in the INTx handling function PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup PCI: mobiveil: Clear the control fields before updating it PCI: mobiveil: Add configured inbound windows counter PCI: mobiveil: Fix the valid check for inbound and outbound windows PCI: mobiveil: Clean-up program_{ib/ob}_windows() PCI: mobiveil: Remove an unnecessary return value check PCI: mobiveil: Fix error return values PCI: mobiveil: Refactor the MEM/IO outbound window initialization PCI: mobiveil: Make some register updates more readable PCI: mobiveil: Reformat the code for readability dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional ...
612 lines
19 KiB
C
612 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DRIVERS_PCI_H
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#define DRIVERS_PCI_H
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#include <linux/pci.h>
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#define PCI_FIND_CAP_TTL 48
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#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
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extern const unsigned char pcie_link_speed[];
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extern bool pci_early_dump;
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
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/* Functions internal to the PCI core code */
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int pci_create_sysfs_dev_files(struct pci_dev *pdev);
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void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
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#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
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static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
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{ return; }
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static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
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{ return; }
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#else
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void pci_create_firmware_label_files(struct pci_dev *pdev);
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void pci_remove_firmware_label_files(struct pci_dev *pdev);
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#endif
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void pci_cleanup_rom(struct pci_dev *dev);
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enum pci_mmap_api {
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PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
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PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
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};
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int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
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enum pci_mmap_api mmap_api);
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int pci_probe_reset_function(struct pci_dev *dev);
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int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
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int pci_bus_error_reset(struct pci_dev *dev);
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/**
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* struct pci_platform_pm_ops - Firmware PM callbacks
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*
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* @bridge_d3: Does the bridge allow entering into D3
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*
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* @is_manageable: returns 'true' if given device is power manageable by the
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* platform firmware
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*
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* @set_state: invokes the platform firmware to set the device's power state
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*
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* @get_state: queries the platform firmware for a device's current power state
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*
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* @refresh_state: asks the platform to refresh the device's power state data
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*
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* @choose_state: returns PCI power state of given device preferred by the
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* platform; to be used during system-wide transitions from a
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* sleeping state to the working state and vice versa
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*
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* @set_wakeup: enables/disables wakeup capability for the device
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*
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* @need_resume: returns 'true' if the given device (which is currently
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* suspended) needs to be resumed to be configured for system
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* wakeup.
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*
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* If given platform is generally capable of power managing PCI devices, all of
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* these callbacks are mandatory.
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*/
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struct pci_platform_pm_ops {
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bool (*bridge_d3)(struct pci_dev *dev);
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bool (*is_manageable)(struct pci_dev *dev);
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int (*set_state)(struct pci_dev *dev, pci_power_t state);
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pci_power_t (*get_state)(struct pci_dev *dev);
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void (*refresh_state)(struct pci_dev *dev);
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pci_power_t (*choose_state)(struct pci_dev *dev);
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int (*set_wakeup)(struct pci_dev *dev, bool enable);
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bool (*need_resume)(struct pci_dev *dev);
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};
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int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
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void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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void pci_refresh_power_state(struct pci_dev *dev);
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void pci_power_up(struct pci_dev *dev);
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void pci_disable_enabled_device(struct pci_dev *dev);
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int pci_finish_runtime_suspend(struct pci_dev *dev);
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void pcie_clear_root_pme_status(struct pci_dev *dev);
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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void pci_pme_restore(struct pci_dev *dev);
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bool pci_dev_need_resume(struct pci_dev *dev);
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void pci_dev_adjust_pme(struct pci_dev *dev);
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void pci_dev_complete_resume(struct pci_dev *pci_dev);
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void pci_config_pm_runtime_get(struct pci_dev *dev);
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void pci_config_pm_runtime_put(struct pci_dev *dev);
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void pci_pm_init(struct pci_dev *dev);
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void pci_ea_init(struct pci_dev *dev);
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void pci_allocate_cap_save_buffers(struct pci_dev *dev);
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void pci_free_cap_save_buffers(struct pci_dev *dev);
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bool pci_bridge_d3_possible(struct pci_dev *dev);
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void pci_bridge_d3_update(struct pci_dev *dev);
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static inline void pci_wakeup_event(struct pci_dev *dev)
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{
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/* Wait 100 ms before the system can be put into a sleep state. */
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pm_wakeup_event(&dev->dev, 100);
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}
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static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
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{
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return !!(pci_dev->subordinate);
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}
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static inline bool pci_power_manageable(struct pci_dev *pci_dev)
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{
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/*
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* Currently we allow normal PCI devices and PCI bridges transition
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* into D3 if their bridge_d3 is set.
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*/
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return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
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}
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int pci_vpd_init(struct pci_dev *dev);
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void pci_vpd_release(struct pci_dev *dev);
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void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
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void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
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/* PCI /proc functions */
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#ifdef CONFIG_PROC_FS
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int pci_proc_attach_device(struct pci_dev *dev);
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int pci_proc_detach_device(struct pci_dev *dev);
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int pci_proc_detach_bus(struct pci_bus *bus);
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#else
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
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#endif
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/* Functions for PCI Hotplug drivers to use */
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int pci_hp_add_bridge(struct pci_dev *dev);
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#ifdef HAVE_PCI_LEGACY
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void pci_create_legacy_files(struct pci_bus *bus);
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void pci_remove_legacy_files(struct pci_bus *bus);
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#else
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static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
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static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
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#endif
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/* Lock for read/write access to pci device and bus lists */
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extern struct rw_semaphore pci_bus_sem;
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extern struct mutex pci_slot_mutex;
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extern raw_spinlock_t pci_lock;
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extern unsigned int pci_pm_d3_delay;
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#ifdef CONFIG_PCI_MSI
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void pci_no_msi(void);
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#else
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static inline void pci_no_msi(void) { }
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#endif
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static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
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{
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u16 control;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
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{
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u16 ctrl;
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
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ctrl &= ~clear;
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ctrl |= set;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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}
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void pci_realloc_get_opt(char *);
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static inline int pci_no_d1d2(struct pci_dev *dev)
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{
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unsigned int parent_dstates = 0;
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if (dev->bus->self)
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parent_dstates = dev->bus->self->no_d1d2;
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return (dev->no_d1d2 || parent_dstates);
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}
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extern const struct attribute_group *pci_dev_groups[];
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extern const struct attribute_group *pcibus_groups[];
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extern const struct device_type pci_dev_type;
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extern const struct attribute_group *pci_bus_groups[];
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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* Returns the matching pci_device_id structure or %NULL if there is no match.
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*/
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static inline const struct pci_device_id *
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
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{
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
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(id->device == PCI_ANY_ID || id->device == dev->device) &&
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
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!((id->class ^ dev->class) & id->class_mask))
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return id;
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return NULL;
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}
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/* PCI slot sysfs helper code */
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#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
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extern struct kset *pci_slots_kset;
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struct pci_slot_attribute {
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struct attribute attr;
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ssize_t (*show)(struct pci_slot *, char *);
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ssize_t (*store)(struct pci_slot *, const char *, size_t);
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};
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#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An I/O port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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void pci_configure_ari(struct pci_dev *dev);
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void __pci_bus_size_bridges(struct pci_bus *bus,
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struct list_head *realloc_head);
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void __pci_bus_assign_resources(const struct pci_bus *bus,
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struct list_head *realloc_head,
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struct list_head *fail_head);
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bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
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void pci_reassigndev_resource_alignment(struct pci_dev *dev);
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void pci_disable_bridge_window(struct pci_dev *dev);
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/* PCIe link information */
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#define PCIE_SPEED2STR(speed) \
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((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
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(speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
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(speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
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(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
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"Unknown speed")
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/* PCIe speed to Mb/s reduced by encoding overhead */
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#define PCIE_SPEED2MBS_ENC(speed) \
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((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
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(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
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(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
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(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
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0)
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enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
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void pcie_report_downtraining(struct pci_dev *dev);
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* Capability position */
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int nres; /* Number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total_VFs; /* Total VFs associated with the PF */
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u16 initial_VFs; /* Initial VFs associated with the PF */
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u16 num_VFs; /* Number of VFs available */
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u16 offset; /* First VF Routing ID offset */
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u16 stride; /* Following VF stride */
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u16 vf_device; /* VF device ID */
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u32 pgsz; /* Page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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u8 max_VF_buses; /* Max buses consumed by VFs */
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u16 driver_max_VFs; /* Max num VFs driver supports */
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struct pci_dev *dev; /* Lowest numbered PF */
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struct pci_dev *self; /* This PF */
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u32 class; /* VF device */
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u8 hdr_type; /* VF header type */
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u16 subsystem_vendor; /* VF subsystem vendor */
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u16 subsystem_device; /* VF subsystem device */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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bool drivers_autoprobe; /* Auto probing of VFs by driver */
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};
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/**
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* pci_dev_set_io_state - Set the new error state if possible.
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*
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* @dev - pci device to set new error_state
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* @new - the state we want dev to be in
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*
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* Must be called with device_lock held.
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*
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* Returns true if state has been changed to the requested state.
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*/
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static inline bool pci_dev_set_io_state(struct pci_dev *dev,
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pci_channel_state_t new)
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{
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bool changed = false;
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device_lock_assert(&dev->dev);
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switch (new) {
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case pci_channel_io_perm_failure:
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switch (dev->error_state) {
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case pci_channel_io_frozen:
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case pci_channel_io_normal:
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case pci_channel_io_perm_failure:
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changed = true;
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break;
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}
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break;
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case pci_channel_io_frozen:
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switch (dev->error_state) {
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case pci_channel_io_frozen:
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case pci_channel_io_normal:
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changed = true;
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break;
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}
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break;
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case pci_channel_io_normal:
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switch (dev->error_state) {
|
|
case pci_channel_io_frozen:
|
|
case pci_channel_io_normal:
|
|
changed = true;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
if (changed)
|
|
dev->error_state = new;
|
|
return changed;
|
|
}
|
|
|
|
static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
|
|
{
|
|
device_lock(&dev->dev);
|
|
pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
|
|
device_unlock(&dev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
|
|
{
|
|
return dev->error_state == pci_channel_io_perm_failure;
|
|
}
|
|
|
|
/* pci_dev priv_flags */
|
|
#define PCI_DEV_ADDED 0
|
|
|
|
static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
|
|
{
|
|
assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
|
|
}
|
|
|
|
static inline bool pci_dev_is_added(const struct pci_dev *dev)
|
|
{
|
|
return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
|
|
}
|
|
|
|
#ifdef CONFIG_PCIEAER
|
|
#include <linux/aer.h>
|
|
|
|
#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
|
|
|
|
struct aer_err_info {
|
|
struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
|
|
int error_dev_num;
|
|
|
|
unsigned int id:16;
|
|
|
|
unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
|
|
unsigned int __pad1:5;
|
|
unsigned int multi_error_valid:1;
|
|
|
|
unsigned int first_error:5;
|
|
unsigned int __pad2:2;
|
|
unsigned int tlp_header_valid:1;
|
|
|
|
unsigned int status; /* COR/UNCOR Error Status */
|
|
unsigned int mask; /* COR/UNCOR Error Mask */
|
|
struct aer_header_log_regs tlp; /* TLP Header */
|
|
};
|
|
|
|
int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
|
|
void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
|
|
#endif /* CONFIG_PCIEAER */
|
|
|
|
#ifdef CONFIG_PCIE_DPC
|
|
void pci_save_dpc_state(struct pci_dev *dev);
|
|
void pci_restore_dpc_state(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_save_dpc_state(struct pci_dev *dev) {}
|
|
static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_ATS
|
|
void pci_restore_ats_state(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_restore_ats_state(struct pci_dev *dev)
|
|
{
|
|
}
|
|
#endif /* CONFIG_PCI_ATS */
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
int pci_iov_init(struct pci_dev *dev);
|
|
void pci_iov_release(struct pci_dev *dev);
|
|
void pci_iov_remove(struct pci_dev *dev);
|
|
void pci_iov_update_resource(struct pci_dev *dev, int resno);
|
|
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
|
|
void pci_restore_iov_state(struct pci_dev *dev);
|
|
int pci_iov_bus_range(struct pci_bus *bus);
|
|
|
|
#else
|
|
static inline int pci_iov_init(struct pci_dev *dev)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void pci_iov_release(struct pci_dev *dev)
|
|
|
|
{
|
|
}
|
|
static inline void pci_iov_remove(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline void pci_restore_iov_state(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline int pci_iov_bus_range(struct pci_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PCI_IOV */
|
|
|
|
unsigned long pci_cardbus_resource_alignment(struct resource *);
|
|
|
|
static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
|
|
struct resource *res)
|
|
{
|
|
#ifdef CONFIG_PCI_IOV
|
|
int resno = res - dev->resource;
|
|
|
|
if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
|
|
return pci_sriov_resource_alignment(dev, resno);
|
|
#endif
|
|
if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
|
|
return pci_cardbus_resource_alignment(res);
|
|
return resource_alignment(res);
|
|
}
|
|
|
|
void pci_enable_acs(struct pci_dev *dev);
|
|
#ifdef CONFIG_PCI_QUIRKS
|
|
int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
|
|
int pci_dev_specific_enable_acs(struct pci_dev *dev);
|
|
int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
|
|
#else
|
|
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
|
|
u16 acs_flags)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
#endif
|
|
|
|
/* PCI error reporting and recovery */
|
|
void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
|
|
u32 service);
|
|
|
|
bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay);
|
|
bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
|
|
#ifdef CONFIG_PCIEASPM
|
|
void pcie_aspm_init_link_state(struct pci_dev *pdev);
|
|
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
|
|
void pcie_aspm_pm_state_change(struct pci_dev *pdev);
|
|
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIEASPM_DEBUG
|
|
void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
|
|
void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
|
|
#else
|
|
static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
|
|
static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_PTM
|
|
void pci_ptm_init(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_ptm_init(struct pci_dev *dev) { }
|
|
#endif
|
|
|
|
struct pci_dev_reset_methods {
|
|
u16 vendor;
|
|
u16 device;
|
|
int (*reset)(struct pci_dev *dev, int probe);
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_QUIRKS
|
|
int pci_dev_specific_reset(struct pci_dev *dev, int probe);
|
|
#else
|
|
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
|
|
{
|
|
return -ENOTTY;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
|
|
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
|
|
struct resource *res);
|
|
#endif
|
|
|
|
u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
|
|
int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
|
|
int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
|
|
static inline u64 pci_rebar_size_to_bytes(int size)
|
|
{
|
|
return 1ULL << (size + 20);
|
|
}
|
|
|
|
struct device_node;
|
|
|
|
#ifdef CONFIG_OF
|
|
int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
|
|
int of_get_pci_domain_nr(struct device_node *node);
|
|
int of_pci_get_max_link_speed(struct device_node *node);
|
|
|
|
#else
|
|
static inline int
|
|
of_pci_parse_bus_range(struct device_node *node, struct resource *res)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline int
|
|
of_get_pci_domain_nr(struct device_node *node)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
static inline int
|
|
of_pci_get_max_link_speed(struct device_node *node)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif /* CONFIG_OF */
|
|
|
|
#if defined(CONFIG_OF_ADDRESS)
|
|
int devm_of_pci_get_host_bridge_resources(struct device *dev,
|
|
unsigned char busno, unsigned char bus_max,
|
|
struct list_head *resources, resource_size_t *io_base);
|
|
#else
|
|
static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
|
|
unsigned char busno, unsigned char bus_max,
|
|
struct list_head *resources, resource_size_t *io_base)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIEAER
|
|
void pci_no_aer(void);
|
|
void pci_aer_init(struct pci_dev *dev);
|
|
void pci_aer_exit(struct pci_dev *dev);
|
|
extern const struct attribute_group aer_stats_attr_group;
|
|
void pci_aer_clear_fatal_status(struct pci_dev *dev);
|
|
void pci_aer_clear_device_status(struct pci_dev *dev);
|
|
#else
|
|
static inline void pci_no_aer(void) { }
|
|
static inline void pci_aer_init(struct pci_dev *d) { }
|
|
static inline void pci_aer_exit(struct pci_dev *d) { }
|
|
static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
|
|
static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
|
|
#endif
|
|
|
|
#endif /* DRIVERS_PCI_H */
|