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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
704 lines
19 KiB
C
704 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Maxim MAX77620 MFD Driver
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*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Laxman Dewangan <ldewangan@nvidia.com>
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* Chaitanya Bandi <bandik@nvidia.com>
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* Mallikarjun Kasoju <mkasoju@nvidia.com>
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*/
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/****************** Teminology used in driver ********************
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* Here are some terminology used from datasheet for quick reference:
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* Flexible Power Sequence (FPS):
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* The Flexible Power Sequencer (FPS) allows each regulator to power up under
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* hardware or software control. Additionally, each regulator can power on
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* independently or among a group of other regulators with an adjustable
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* power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
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* be programmed to be part of a sequence allowing external regulators to be
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* sequenced along with internal regulators. 32KHz clock can be programmed to
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* be part of a sequence.
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* There is 3 FPS confguration registers and all resources are configured to
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* any of these FPS or no FPS.
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*/
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/max77620.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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static struct max77620_chip *max77620_scratch;
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static const struct resource gpio_resources[] = {
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DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
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};
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static const struct resource power_resources[] = {
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DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
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};
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static const struct resource rtc_resources[] = {
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DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
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};
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static const struct resource thermal_resources[] = {
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DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
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DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
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};
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static const struct regmap_irq max77620_top_irqs[] = {
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
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REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
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};
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static const struct mfd_cell max77620_children[] = {
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{ .name = "max77620-pinctrl", },
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{ .name = "max77620-clock", },
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{ .name = "max77620-pmic", },
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{ .name = "max77620-watchdog", },
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{
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.name = "max77620-gpio",
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.resources = gpio_resources,
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.num_resources = ARRAY_SIZE(gpio_resources),
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}, {
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.name = "max77620-rtc",
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.resources = rtc_resources,
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.num_resources = ARRAY_SIZE(rtc_resources),
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}, {
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.name = "max77620-power",
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.resources = power_resources,
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.num_resources = ARRAY_SIZE(power_resources),
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}, {
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.name = "max77620-thermal",
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.resources = thermal_resources,
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.num_resources = ARRAY_SIZE(thermal_resources),
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},
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};
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static const struct mfd_cell max20024_children[] = {
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{ .name = "max20024-pinctrl", },
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{ .name = "max77620-clock", },
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{ .name = "max20024-pmic", },
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{ .name = "max77620-watchdog", },
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{
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.name = "max77620-gpio",
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.resources = gpio_resources,
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.num_resources = ARRAY_SIZE(gpio_resources),
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}, {
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.name = "max77620-rtc",
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.resources = rtc_resources,
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.num_resources = ARRAY_SIZE(rtc_resources),
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}, {
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.name = "max20024-power",
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.resources = power_resources,
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.num_resources = ARRAY_SIZE(power_resources),
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},
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};
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static const struct mfd_cell max77663_children[] = {
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{ .name = "max77620-pinctrl", },
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{ .name = "max77620-clock", },
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{ .name = "max77663-pmic", },
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{ .name = "max77620-watchdog", },
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{
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.name = "max77620-gpio",
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.resources = gpio_resources,
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.num_resources = ARRAY_SIZE(gpio_resources),
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}, {
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.name = "max77620-rtc",
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.resources = rtc_resources,
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.num_resources = ARRAY_SIZE(rtc_resources),
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}, {
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.name = "max77663-power",
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.resources = power_resources,
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.num_resources = ARRAY_SIZE(power_resources),
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},
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};
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static const struct regmap_range max77620_readable_ranges[] = {
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regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
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};
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static const struct regmap_access_table max77620_readable_table = {
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.yes_ranges = max77620_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
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};
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static const struct regmap_range max20024_readable_ranges[] = {
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regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
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regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
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};
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static const struct regmap_access_table max20024_readable_table = {
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.yes_ranges = max20024_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
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};
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static const struct regmap_range max77620_writable_ranges[] = {
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regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
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};
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static const struct regmap_access_table max77620_writable_table = {
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.yes_ranges = max77620_writable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
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};
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static const struct regmap_range max77620_cacheable_ranges[] = {
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regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
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regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
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};
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static const struct regmap_access_table max77620_volatile_table = {
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.no_ranges = max77620_cacheable_ranges,
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.n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
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};
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static const struct regmap_config max77620_regmap_config = {
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.name = "power-slave",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MAX77620_REG_DVSSD4 + 1,
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.cache_type = REGCACHE_RBTREE,
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.rd_table = &max77620_readable_table,
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.wr_table = &max77620_writable_table,
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.volatile_table = &max77620_volatile_table,
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};
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static const struct regmap_config max20024_regmap_config = {
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.name = "power-slave",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MAX20024_REG_MAX_ADD + 1,
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.cache_type = REGCACHE_RBTREE,
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.rd_table = &max20024_readable_table,
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.wr_table = &max77620_writable_table,
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.volatile_table = &max77620_volatile_table,
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};
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static const struct regmap_range max77663_readable_ranges[] = {
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regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
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};
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static const struct regmap_access_table max77663_readable_table = {
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.yes_ranges = max77663_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
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};
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static const struct regmap_range max77663_writable_ranges[] = {
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regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
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};
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static const struct regmap_access_table max77663_writable_table = {
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.yes_ranges = max77663_writable_ranges,
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.n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
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};
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static const struct regmap_config max77663_regmap_config = {
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.name = "power-slave",
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MAX77620_REG_CID5 + 1,
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.cache_type = REGCACHE_RBTREE,
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.rd_table = &max77663_readable_table,
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.wr_table = &max77663_writable_table,
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.volatile_table = &max77620_volatile_table,
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};
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/*
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* MAX77620 and MAX20024 has the following steps of the interrupt handling
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* for TOP interrupts:
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* 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
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* 2. Read IRQTOP and service the interrupt.
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* 3. Once all interrupts has been checked and serviced, the interrupt service
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* routine un-masks the hardware interrupt line by clearing GLBLM.
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*/
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static int max77620_irq_global_mask(void *irq_drv_data)
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{
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struct max77620_chip *chip = irq_drv_data;
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int ret;
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ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
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MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
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if (ret < 0)
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dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
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return ret;
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}
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static int max77620_irq_global_unmask(void *irq_drv_data)
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{
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struct max77620_chip *chip = irq_drv_data;
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int ret;
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ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
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MAX77620_GLBLM_MASK, 0);
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if (ret < 0)
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dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
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return ret;
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}
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static struct regmap_irq_chip max77620_top_irq_chip = {
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.name = "max77620-top",
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.irqs = max77620_top_irqs,
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.num_irqs = ARRAY_SIZE(max77620_top_irqs),
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.num_regs = 2,
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.status_base = MAX77620_REG_IRQTOP,
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.mask_base = MAX77620_REG_IRQTOPM,
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.handle_pre_irq = max77620_irq_global_mask,
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.handle_post_irq = max77620_irq_global_unmask,
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};
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/* max77620_get_fps_period_reg_value: Get FPS bit field value from
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* requested periods.
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* MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
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* and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
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* 160, 320, 540, 1280 and 2560 microseconds.
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* The FPS register has 3 bits field to set the FPS period as
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* bits max77620 max20024
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* 000 40 20
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* 001 80 40
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* :::
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*/
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static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
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int tperiod)
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{
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int fps_min_period;
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int i;
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switch (chip->chip_id) {
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case MAX20024:
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fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
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break;
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case MAX77620:
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fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
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break;
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case MAX77663:
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fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < 7; i++) {
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if (fps_min_period >= tperiod)
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return i;
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fps_min_period *= 2;
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}
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return i;
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}
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/* max77620_config_fps: Configure FPS configuration registers
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* based on platform specific information.
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*/
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static int max77620_config_fps(struct max77620_chip *chip,
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struct device_node *fps_np)
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{
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struct device *dev = chip->dev;
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unsigned int mask = 0, config = 0;
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u32 fps_max_period;
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u32 param_val;
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int tperiod, fps_id;
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int ret;
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char fps_name[10];
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switch (chip->chip_id) {
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case MAX20024:
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fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
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break;
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case MAX77620:
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fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
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break;
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case MAX77663:
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fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
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break;
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default:
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return -EINVAL;
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}
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for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
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sprintf(fps_name, "fps%d", fps_id);
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if (of_node_name_eq(fps_np, fps_name))
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break;
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}
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if (fps_id == MAX77620_FPS_COUNT) {
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dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
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return -EINVAL;
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}
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ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
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¶m_val);
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if (!ret) {
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mask |= MAX77620_FPS_TIME_PERIOD_MASK;
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chip->shutdown_fps_period[fps_id] = min(param_val,
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fps_max_period);
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tperiod = max77620_get_fps_period_reg_value(chip,
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chip->shutdown_fps_period[fps_id]);
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config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
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}
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ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
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¶m_val);
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if (!ret)
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chip->suspend_fps_period[fps_id] = min(param_val,
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fps_max_period);
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ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
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¶m_val);
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if (!ret) {
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if (param_val > 2) {
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dev_err(dev, "FPS%d event-source invalid\n", fps_id);
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return -EINVAL;
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}
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mask |= MAX77620_FPS_EN_SRC_MASK;
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config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
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if (param_val == 2) {
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mask |= MAX77620_FPS_ENFPS_SW_MASK;
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config |= MAX77620_FPS_ENFPS_SW;
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}
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}
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if (!chip->sleep_enable && !chip->enable_global_lpm) {
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ret = of_property_read_u32(fps_np,
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"maxim,device-state-on-disabled-event",
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¶m_val);
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if (!ret) {
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if (param_val == 0)
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chip->sleep_enable = true;
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else if (param_val == 1)
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chip->enable_global_lpm = true;
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}
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}
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ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
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mask, config);
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if (ret < 0) {
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dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int max77620_initialise_fps(struct max77620_chip *chip)
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{
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struct device *dev = chip->dev;
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struct device_node *fps_np, *fps_child;
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u8 config;
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int fps_id;
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int ret;
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for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
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chip->shutdown_fps_period[fps_id] = -1;
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chip->suspend_fps_period[fps_id] = -1;
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}
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fps_np = of_get_child_by_name(dev->of_node, "fps");
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if (!fps_np)
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goto skip_fps;
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for_each_child_of_node(fps_np, fps_child) {
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ret = max77620_config_fps(chip, fps_child);
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if (ret < 0)
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return ret;
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}
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config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
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ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
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MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
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if (ret < 0) {
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dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
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return ret;
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}
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skip_fps:
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if (chip->chip_id == MAX77663)
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return 0;
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/* Enable wake on EN0 pin */
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ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
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MAX77620_ONOFFCNFG2_WK_EN0,
|
|
MAX77620_ONOFFCNFG2_WK_EN0);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
|
|
if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
|
|
config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
|
|
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
|
|
config, config);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to update SLPEN: %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int max77620_read_es_version(struct max77620_chip *chip)
|
|
{
|
|
unsigned int val;
|
|
u8 cid_val[6];
|
|
int i;
|
|
int ret;
|
|
|
|
for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
|
|
ret = regmap_read(chip->rmap, i, &val);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Failed to read CID: %d\n", ret);
|
|
return ret;
|
|
}
|
|
dev_dbg(chip->dev, "CID%d: 0x%02x\n",
|
|
i - MAX77620_REG_CID0, val);
|
|
cid_val[i - MAX77620_REG_CID0] = val;
|
|
}
|
|
|
|
/* CID4 is OTP Version and CID5 is ES version */
|
|
dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
|
|
cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void max77620_pm_power_off(void)
|
|
{
|
|
struct max77620_chip *chip = max77620_scratch;
|
|
|
|
regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
|
|
MAX77620_ONOFFCNFG1_SFT_RST,
|
|
MAX77620_ONOFFCNFG1_SFT_RST);
|
|
}
|
|
|
|
static int max77620_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
const struct regmap_config *rmap_config;
|
|
struct max77620_chip *chip;
|
|
const struct mfd_cell *mfd_cells;
|
|
int n_mfd_cells;
|
|
bool pm_off;
|
|
int ret;
|
|
|
|
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
i2c_set_clientdata(client, chip);
|
|
chip->dev = &client->dev;
|
|
chip->irq_base = -1;
|
|
chip->chip_irq = client->irq;
|
|
chip->chip_id = (enum max77620_chip_id)id->driver_data;
|
|
|
|
switch (chip->chip_id) {
|
|
case MAX77620:
|
|
mfd_cells = max77620_children;
|
|
n_mfd_cells = ARRAY_SIZE(max77620_children);
|
|
rmap_config = &max77620_regmap_config;
|
|
break;
|
|
case MAX20024:
|
|
mfd_cells = max20024_children;
|
|
n_mfd_cells = ARRAY_SIZE(max20024_children);
|
|
rmap_config = &max20024_regmap_config;
|
|
break;
|
|
case MAX77663:
|
|
mfd_cells = max77663_children;
|
|
n_mfd_cells = ARRAY_SIZE(max77663_children);
|
|
rmap_config = &max77663_regmap_config;
|
|
break;
|
|
default:
|
|
dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->rmap = devm_regmap_init_i2c(client, rmap_config);
|
|
if (IS_ERR(chip->rmap)) {
|
|
ret = PTR_ERR(chip->rmap);
|
|
dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = max77620_read_es_version(chip);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
max77620_top_irq_chip.irq_drv_data = chip;
|
|
ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
|
|
IRQF_ONESHOT | IRQF_SHARED,
|
|
chip->irq_base, &max77620_top_irq_chip,
|
|
&chip->top_irq_data);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = max77620_initialise_fps(chip);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
|
|
mfd_cells, n_mfd_cells, NULL, 0,
|
|
regmap_irq_get_domain(chip->top_irq_data));
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pm_off = of_device_is_system_power_controller(client->dev.of_node);
|
|
if (pm_off && !pm_power_off) {
|
|
max77620_scratch = chip;
|
|
pm_power_off = max77620_pm_power_off;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int max77620_set_fps_period(struct max77620_chip *chip,
|
|
int fps_id, int time_period)
|
|
{
|
|
int period = max77620_get_fps_period_reg_value(chip, time_period);
|
|
int ret;
|
|
|
|
ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
|
|
MAX77620_FPS_TIME_PERIOD_MASK,
|
|
period << MAX77620_FPS_TIME_PERIOD_SHIFT);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int max77620_i2c_suspend(struct device *dev)
|
|
{
|
|
struct max77620_chip *chip = dev_get_drvdata(dev);
|
|
struct i2c_client *client = to_i2c_client(dev);
|
|
unsigned int config;
|
|
int fps;
|
|
int ret;
|
|
|
|
for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
|
|
if (chip->suspend_fps_period[fps] < 0)
|
|
continue;
|
|
|
|
ret = max77620_set_fps_period(chip, fps,
|
|
chip->suspend_fps_period[fps]);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* For MAX20024: No need to configure SLPEN on suspend as
|
|
* it will be configured on Init.
|
|
*/
|
|
if (chip->chip_id == MAX20024)
|
|
goto out;
|
|
|
|
config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
|
|
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
|
|
MAX77620_ONOFFCNFG1_SLPEN,
|
|
config);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (chip->chip_id == MAX77663)
|
|
goto out;
|
|
|
|
/* Disable WK_EN0 */
|
|
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
|
|
MAX77620_ONOFFCNFG2_WK_EN0, 0);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
out:
|
|
disable_irq(client->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int max77620_i2c_resume(struct device *dev)
|
|
{
|
|
struct max77620_chip *chip = dev_get_drvdata(dev);
|
|
struct i2c_client *client = to_i2c_client(dev);
|
|
int ret;
|
|
int fps;
|
|
|
|
for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
|
|
if (chip->shutdown_fps_period[fps] < 0)
|
|
continue;
|
|
|
|
ret = max77620_set_fps_period(chip, fps,
|
|
chip->shutdown_fps_period[fps]);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* For MAX20024: No need to configure WKEN0 on resume as
|
|
* it is configured on Init.
|
|
*/
|
|
if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
|
|
goto out;
|
|
|
|
/* Enable WK_EN0 */
|
|
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
|
|
MAX77620_ONOFFCNFG2_WK_EN0,
|
|
MAX77620_ONOFFCNFG2_WK_EN0);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
out:
|
|
enable_irq(client->irq);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct i2c_device_id max77620_id[] = {
|
|
{"max77620", MAX77620},
|
|
{"max20024", MAX20024},
|
|
{"max77663", MAX77663},
|
|
{},
|
|
};
|
|
|
|
static const struct dev_pm_ops max77620_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
|
|
};
|
|
|
|
static struct i2c_driver max77620_driver = {
|
|
.driver = {
|
|
.name = "max77620",
|
|
.pm = &max77620_pm_ops,
|
|
},
|
|
.probe = max77620_probe,
|
|
.id_table = max77620_id,
|
|
};
|
|
builtin_i2c_driver(max77620_driver);
|