mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 10:36:51 +07:00
57f4959bad
'User Access Override' is a new ARMv8.2 feature which allows the
unprivileged load and store instructions to be overridden to behave in
the normal way.
This patch converts {get,put}_user() and friends to use ldtr*/sttr*
instructions - so that they can only access EL0 memory, then enables
UAO when fs==KERNEL_DS so that these functions can access kernel memory.
This allows user space's read/write permissions to be checked against the
page tables, instead of testing addr<USER_DS, then using the kernel's
read/write permissions.
Signed-off-by: James Morse <james.morse@arm.com>
[catalin.marinas@arm.com: move uao_thread_switch() above dsb()]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
197 lines
4.8 KiB
C
197 lines
4.8 KiB
C
/*
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* Based on arch/arm/include/asm/processor.h
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*
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* Copyright (C) 1995-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PROCESSOR_H
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#define __ASM_PROCESSOR_H
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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#ifdef __KERNEL__
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#include <linux/string.h>
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#include <asm/alternative.h>
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#include <asm/fpsimd.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/lse.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#ifdef __KERNEL__
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#define STACK_TOP_MAX TASK_SIZE_64
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#ifdef CONFIG_COMPAT
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#define AARCH32_VECTORS_BASE 0xffff0000
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#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
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AARCH32_VECTORS_BASE : STACK_TOP_MAX)
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#else
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#define STACK_TOP STACK_TOP_MAX
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#endif /* CONFIG_COMPAT */
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extern phys_addr_t arm64_dma_phys_limit;
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#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
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#endif /* __KERNEL__ */
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struct debug_info {
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/* Have we suspended stepping by a debugger? */
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int suspended_step;
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/* Allow breakpoints and watchpoints to be disabled for this thread. */
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int bps_disabled;
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int wps_disabled;
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/* Hardware breakpoints pinned to this task. */
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struct perf_event *hbp_break[ARM_MAX_BRP];
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struct perf_event *hbp_watch[ARM_MAX_WRP];
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};
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struct cpu_context {
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unsigned long x19;
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unsigned long x20;
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unsigned long x21;
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unsigned long x22;
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unsigned long x23;
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unsigned long x24;
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unsigned long x25;
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unsigned long x26;
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unsigned long x27;
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unsigned long x28;
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unsigned long fp;
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unsigned long sp;
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unsigned long pc;
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};
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struct thread_struct {
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struct cpu_context cpu_context; /* cpu context */
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unsigned long tp_value; /* TLS register */
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#ifdef CONFIG_COMPAT
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unsigned long tp2_value;
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#endif
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struct fpsimd_state fpsimd_state;
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unsigned long fault_address; /* fault info */
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unsigned long fault_code; /* ESR_EL1 value */
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struct debug_info debug; /* debugging */
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};
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#ifdef CONFIG_COMPAT
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#define task_user_tls(t) \
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({ \
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unsigned long *__tls; \
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if (is_compat_thread(task_thread_info(t))) \
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__tls = &(t)->thread.tp2_value; \
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else \
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__tls = &(t)->thread.tp_value; \
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__tls; \
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})
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#else
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#define task_user_tls(t) (&(t)->thread.tp_value)
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#endif
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#define INIT_THREAD { }
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static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
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{
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memset(regs, 0, sizeof(*regs));
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regs->syscallno = ~0UL;
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regs->pc = pc;
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}
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static inline void start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = PSR_MODE_EL0t;
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regs->sp = sp;
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}
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#ifdef CONFIG_COMPAT
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static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = COMPAT_PSR_MODE_USR;
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if (pc & 1)
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regs->pstate |= COMPAT_PSR_T_BIT;
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#ifdef __AARCH64EB__
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regs->pstate |= COMPAT_PSR_E_BIT;
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#endif
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regs->compat_sp = sp;
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}
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#endif
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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unsigned long get_wchan(struct task_struct *p);
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static inline void cpu_relax(void)
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{
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asm volatile("yield" ::: "memory");
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}
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#define cpu_relax_lowlatency() cpu_relax()
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/* Thread switching */
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extern struct task_struct *cpu_switch_to(struct task_struct *prev,
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struct task_struct *next);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
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#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
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/*
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* Prefetching support
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*/
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *ptr)
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{
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asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_PREFETCHW
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static inline void prefetchw(const void *ptr)
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{
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asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void spin_lock_prefetch(const void *ptr)
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{
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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"prfm pstl1strm, %a0",
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"nop") : : "p" (ptr));
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}
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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#endif
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void cpu_enable_pan(void *__unused);
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void cpu_enable_uao(void *__unused);
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#endif /* __ASM_PROCESSOR_H */
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