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28c5dcb22f
Now that we have a clear understanding of the sign of a feature, rename the routines to reflect the sign, so that it is not misused. The cpuid_feature_extract_field() now accepts a 'sign' parameter. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
315 lines
8.9 KiB
C
315 lines
8.9 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_MMU_H__
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#define __ARM64_KVM_MMU_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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#include <asm/cpufeature.h>
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/*
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* As we only have the TTBR0_EL2 register, we cannot express
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* "negative" addresses. This makes it impossible to directly share
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* mappings with the kernel.
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*
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* Instead, give the HYP mode its own VA region at a fixed offset from
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* the kernel by just masking the top bits (which are all ones for a
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* kernel address).
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*/
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#define HYP_PAGE_OFFSET_SHIFT VA_BITS
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#define HYP_PAGE_OFFSET_MASK ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
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#define HYP_PAGE_OFFSET (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
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/*
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* Our virtual mapping for the idmap-ed MMU-enable code. Must be
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* shared across all the page-tables. Conveniently, we use the last
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* possible page, where no kernel mapping will ever exist.
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*/
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#define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
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/*
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* KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation
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* levels in addition to the PGD and potentially the PUD which are
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* pre-allocated (we pre-allocate the fake PGD and the PUD when the Stage-2
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* tables use one level of tables less than the kernel.
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*/
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#ifdef CONFIG_ARM64_64K_PAGES
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#define KVM_MMU_CACHE_MIN_PAGES 1
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#else
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#define KVM_MMU_CACHE_MIN_PAGES 2
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#endif
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#ifdef __ASSEMBLY__
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/*
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* Convert a kernel VA into a HYP VA.
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* reg: VA to be converted.
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*/
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.macro kern_hyp_va reg
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and \reg, \reg, #HYP_PAGE_OFFSET_MASK
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.endm
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#else
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#include <asm/pgalloc.h>
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#include <asm/cachetype.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#define KERN_TO_HYP(kva) ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
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/*
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* We currently only support a 40bit IPA.
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*/
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#define KVM_PHYS_SHIFT (40)
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#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT)
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#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL)
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int create_hyp_mappings(void *from, void *to);
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int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
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void free_boot_hyp_pgd(void);
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void free_hyp_pgds(void);
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void stage2_unmap_vm(struct kvm *kvm);
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int kvm_alloc_stage2_pgd(struct kvm *kvm);
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void kvm_free_stage2_pgd(struct kvm *kvm);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size, bool writable);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_mmu_get_boot_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
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#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
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static inline void kvm_clean_pgd(pgd_t *pgd) {}
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static inline void kvm_clean_pmd(pmd_t *pmd) {}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
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static inline void kvm_clean_pte(pte_t *pte) {}
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static inline void kvm_clean_pte_entry(pte_t *pte) {}
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static inline void kvm_set_s2pte_writable(pte_t *pte)
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{
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pte_val(*pte) |= PTE_S2_RDWR;
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}
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static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
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{
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pmd_val(*pmd) |= PMD_S2_RDWR;
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}
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static inline void kvm_set_s2pte_readonly(pte_t *pte)
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{
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pte_val(*pte) = (pte_val(*pte) & ~PTE_S2_RDWR) | PTE_S2_RDONLY;
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}
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static inline bool kvm_s2pte_readonly(pte_t *pte)
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{
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return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY;
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}
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static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
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{
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pmd_val(*pmd) = (pmd_val(*pmd) & ~PMD_S2_RDWR) | PMD_S2_RDONLY;
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}
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static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
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{
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return (pmd_val(*pmd) & PMD_S2_RDWR) == PMD_S2_RDONLY;
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}
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#define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end)
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#define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end)
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#define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end)
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/*
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* In the case where PGDIR_SHIFT is larger than KVM_PHYS_SHIFT, we can address
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* the entire IPA input range with a single pgd entry, and we would only need
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* one pgd entry. Note that in this case, the pgd is actually not used by
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* the MMU for Stage-2 translations, but is merely a fake pgd used as a data
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* structure for the kernel pgtable macros to work.
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*/
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#if PGDIR_SHIFT > KVM_PHYS_SHIFT
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#define PTRS_PER_S2_PGD_SHIFT 0
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#else
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#define PTRS_PER_S2_PGD_SHIFT (KVM_PHYS_SHIFT - PGDIR_SHIFT)
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#endif
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#define PTRS_PER_S2_PGD (1 << PTRS_PER_S2_PGD_SHIFT)
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#define kvm_pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1))
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/*
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* If we are concatenating first level stage-2 page tables, we would have less
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* than or equal to 16 pointers in the fake PGD, because that's what the
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* architecture allows. In this case, (4 - CONFIG_PGTABLE_LEVELS)
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* represents the first level for the host, and we add 1 to go to the next
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* level (which uses contatenation) for the stage-2 tables.
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*/
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#if PTRS_PER_S2_PGD <= 16
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#define KVM_PREALLOC_LEVEL (4 - CONFIG_PGTABLE_LEVELS + 1)
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#else
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#define KVM_PREALLOC_LEVEL (0)
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#endif
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static inline void *kvm_get_hwpgd(struct kvm *kvm)
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{
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pgd_t *pgd = kvm->arch.pgd;
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pud_t *pud;
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if (KVM_PREALLOC_LEVEL == 0)
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return pgd;
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pud = pud_offset(pgd, 0);
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if (KVM_PREALLOC_LEVEL == 1)
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return pud;
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BUG_ON(KVM_PREALLOC_LEVEL != 2);
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return pmd_offset(pud, 0);
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}
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static inline unsigned int kvm_get_hwpgd_size(void)
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{
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if (KVM_PREALLOC_LEVEL > 0)
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return PTRS_PER_S2_PGD * PAGE_SIZE;
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return PTRS_PER_S2_PGD * sizeof(pgd_t);
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}
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static inline bool kvm_page_empty(void *ptr)
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{
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struct page *ptr_page = virt_to_page(ptr);
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return page_count(ptr_page) == 1;
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}
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#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
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#ifdef __PAGETABLE_PMD_FOLDED
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#define kvm_pmd_table_empty(kvm, pmdp) (0)
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#else
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#define kvm_pmd_table_empty(kvm, pmdp) \
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(kvm_page_empty(pmdp) && (!(kvm) || KVM_PREALLOC_LEVEL < 2))
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#endif
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#ifdef __PAGETABLE_PUD_FOLDED
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#define kvm_pud_table_empty(kvm, pudp) (0)
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#else
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#define kvm_pud_table_empty(kvm, pudp) \
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(kvm_page_empty(pudp) && (!(kvm) || KVM_PREALLOC_LEVEL < 1))
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#endif
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
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}
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static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu,
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kvm_pfn_t pfn,
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unsigned long size,
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bool ipa_uncached)
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{
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void *va = page_address(pfn_to_page(pfn));
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if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
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kvm_flush_dcache_to_poc(va, size);
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if (!icache_is_aliasing()) { /* PIPT */
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flush_icache_range((unsigned long)va,
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(unsigned long)va + size);
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} else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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static inline void __kvm_flush_dcache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
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}
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static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
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{
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struct page *page = pmd_page(pmd);
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kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
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}
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static inline void __kvm_flush_dcache_pud(pud_t pud)
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{
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struct page *page = pud_page(pud);
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kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
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}
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#define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
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void kvm_set_way_flush(struct kvm_vcpu *vcpu);
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void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
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static inline bool __kvm_cpu_uses_extended_idmap(void)
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{
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return __cpu_uses_extended_idmap();
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}
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static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
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pgd_t *hyp_pgd,
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pgd_t *merged_hyp_pgd,
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unsigned long hyp_idmap_start)
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{
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int idmap_idx;
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/*
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* Use the first entry to access the HYP mappings. It is
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* guaranteed to be free, otherwise we wouldn't use an
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* extended idmap.
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*/
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VM_BUG_ON(pgd_val(merged_hyp_pgd[0]));
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merged_hyp_pgd[0] = __pgd(__pa(hyp_pgd) | PMD_TYPE_TABLE);
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/*
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* Create another extended level entry that points to the boot HYP map,
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* which contains an ID mapping of the HYP init code. We essentially
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* merge the boot and runtime HYP maps by doing so, but they don't
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* overlap anyway, so this is fine.
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*/
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idmap_idx = hyp_idmap_start >> VA_BITS;
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VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx]));
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merged_hyp_pgd[idmap_idx] = __pgd(__pa(boot_hyp_pgd) | PMD_TYPE_TABLE);
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}
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static inline unsigned int kvm_get_vmid_bits(void)
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{
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int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1);
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return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ARM64_KVM_MMU_H__ */
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