mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 08:36:47 +07:00
300 lines
6.4 KiB
C
300 lines
6.4 KiB
C
/*
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* Blackfin power management
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*
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* Copyright 2006-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2
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* based on arm/mach-omap/pm.c
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* Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
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*/
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/cplb.h>
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#include <asm/gpio.h>
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#include <asm/dma.h>
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#include <asm/dpmc.h>
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#include <asm/pm.h>
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#ifdef CONFIG_BF60x
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struct bfin_cpu_pm_fns *bfin_cpu_pm;
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#endif
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void bfin_pm_suspend_standby_enter(void)
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{
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#if !BFIN_GPIO_PINT
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bfin_pm_standby_setup();
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#endif
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#ifdef CONFIG_BF60x
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bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
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#else
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# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
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sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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# else
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sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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# endif
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#endif
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#if !BFIN_GPIO_PINT
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bfin_pm_standby_restore();
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#endif
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#ifndef CONFIG_BF60x
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
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# ifdef SIC_IWR1
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/* BF52x system reset does not properly reset SIC_IWR1 which
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* will screw up the bootrom as it relies on MDMA0/1 waking it
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* up from IDLE instructions. See this report for more info:
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* http://blackfin.uclinux.org/gf/tracker/4323
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*/
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if (ANOMALY_05000435)
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bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
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else
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bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
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# endif
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
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# endif
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#else
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bfin_write_SIC_IWR(IWR_DISABLE_ALL);
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#endif
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#endif
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}
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int bf53x_suspend_l1_mem(unsigned char *memptr)
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{
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dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
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L1_CODE_LENGTH);
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dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
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(const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
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dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
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(const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
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memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
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L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
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L1_SCRATCH_LENGTH);
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return 0;
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}
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int bf53x_resume_l1_mem(unsigned char *memptr)
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{
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dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
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dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
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L1_DATA_A_LENGTH);
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dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
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memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
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return 0;
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}
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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# ifdef CONFIG_BF60x
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__attribute__((l1_text))
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# endif
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static void flushinv_all_dcache(void)
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{
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register u32 way, bank, subbank, set;
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register u32 status, addr;
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u32 dmem_ctl = bfin_read_DMEM_CONTROL();
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for (bank = 0; bank < 2; ++bank) {
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if (!(dmem_ctl & (1 << (DMC1_P - bank))))
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continue;
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for (way = 0; way < 2; ++way)
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for (subbank = 0; subbank < 4; ++subbank)
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for (set = 0; set < 64; ++set) {
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bfin_write_DTEST_COMMAND(
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way << 26 |
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bank << 23 |
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subbank << 16 |
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set << 5
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);
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CSYNC();
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status = bfin_read_DTEST_DATA0();
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/* only worry about valid/dirty entries */
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if ((status & 0x3) != 0x3)
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continue;
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/* construct the address using the tag */
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addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
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/* flush it */
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__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
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}
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}
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}
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#endif
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int bfin_pm_suspend_mem_enter(void)
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{
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int ret;
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#ifndef CONFIG_BF60x
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int wakeup;
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#endif
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unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
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+ L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
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GFP_ATOMIC);
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if (memptr == NULL) {
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panic("bf53x_suspend_l1_mem malloc failed");
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return -ENOMEM;
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}
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#ifndef CONFIG_BF60x
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wakeup = bfin_read_VR_CTL() & ~FREQ;
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wakeup |= SCKELOW;
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#ifdef CONFIG_PM_BFIN_WAKE_PH6
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wakeup |= PHYWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_GP
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wakeup |= GPWE;
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#endif
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#endif
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ret = blackfin_dma_suspend();
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if (ret) {
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kfree(memptr);
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return ret;
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}
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#ifdef CONFIG_GPIO_ADI
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bfin_gpio_pm_hibernate_suspend();
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#endif
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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flushinv_all_dcache();
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#endif
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_disable_dcplb();
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_disable_icplb();
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bf53x_suspend_l1_mem(memptr);
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#ifndef CONFIG_BF60x
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do_hibernate(wakeup | vr_wakeup); /* See you later! */
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#else
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bfin_cpu_pm->enter(PM_SUSPEND_MEM);
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#endif
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bf53x_resume_l1_mem(memptr);
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_enable_icplb();
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_enable_dcplb();
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#ifdef CONFIG_GPIO_ADI
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bfin_gpio_pm_hibernate_restore();
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#endif
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blackfin_dma_resume();
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kfree(memptr);
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return 0;
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}
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/*
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* bfin_pm_valid - Tell the PM core that we only support the standby sleep
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* state
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* @state: suspend state we're checking.
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*
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*/
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static int bfin_pm_valid(suspend_state_t state)
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{
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return (state == PM_SUSPEND_STANDBY
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#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
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/*
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* On BF533/2/1:
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* If we enter Hibernate the SCKE Pin is driven Low,
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* so that the SDRAM enters Self Refresh Mode.
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* However when the reset sequence that follows hibernate
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* state is executed, SCKE is driven High, taking the
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* SDRAM out of Self Refresh.
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*
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* If you reconfigure and access the SDRAM "very quickly",
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* you are likely to avoid errors, otherwise the SDRAM
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* start losing its contents.
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* An external HW workaround is possible using logic gates.
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*/
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|| state == PM_SUSPEND_MEM
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#endif
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);
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}
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/*
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* bfin_pm_enter - Actually enter a sleep state.
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* @state: State we're entering.
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*
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*/
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static int bfin_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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bfin_pm_suspend_standby_enter();
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break;
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case PM_SUSPEND_MEM:
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bfin_pm_suspend_mem_enter();
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
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void bfin_pm_end(void)
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{
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u32 cycle, cycle2;
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u64 usec64;
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u32 usec;
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__asm__ __volatile__ (
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"1: %0 = CYCLES2\n"
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"%1 = CYCLES\n"
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"%2 = CYCLES2\n"
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"CC = %2 == %0\n"
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"if ! CC jump 1b\n"
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: "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
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);
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usec64 = ((u64)cycle2 << 32) + cycle;
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do_div(usec64, get_cclk() / USEC_PER_SEC);
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usec = usec64;
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if (usec == 0)
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usec = 1;
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pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
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usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
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}
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#endif
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static const struct platform_suspend_ops bfin_pm_ops = {
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.enter = bfin_pm_enter,
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.valid = bfin_pm_valid,
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#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
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.end = bfin_pm_end,
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#endif
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};
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static int __init bfin_pm_init(void)
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{
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suspend_set_ops(&bfin_pm_ops);
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return 0;
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}
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__initcall(bfin_pm_init);
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