mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 11:06:40 +07:00
f88704c95b
Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Grant Likely <grant.likely@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-6-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
648 lines
16 KiB
C
648 lines
16 KiB
C
/*
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* arch/arm/plat-orion/gpio.c
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*
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* Marvell Orion SoC GPIO handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/leds.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <plat/orion-gpio.h>
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/*
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* GPIO unit register offsets.
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*/
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#define GPIO_OUT_OFF 0x0000
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#define GPIO_IO_CONF_OFF 0x0004
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#define GPIO_BLINK_EN_OFF 0x0008
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#define GPIO_IN_POL_OFF 0x000c
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#define GPIO_DATA_IN_OFF 0x0010
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#define GPIO_EDGE_CAUSE_OFF 0x0014
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#define GPIO_EDGE_MASK_OFF 0x0018
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#define GPIO_LEVEL_MASK_OFF 0x001c
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struct orion_gpio_chip {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *base;
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unsigned long valid_input;
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unsigned long valid_output;
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int mask_offset;
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int secondary_irq_base;
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struct irq_domain *domain;
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};
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static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_OUT_OFF;
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}
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static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_IO_CONF_OFF;
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}
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static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_BLINK_EN_OFF;
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}
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static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_IN_POL_OFF;
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}
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static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_DATA_IN_OFF;
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}
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static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
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{
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return ochip->base + GPIO_EDGE_CAUSE_OFF;
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}
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static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
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{
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return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
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}
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static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
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{
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return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
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}
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static struct orion_gpio_chip orion_gpio_chips[2];
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static int orion_gpio_chip_count;
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static inline void
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__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
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{
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u32 u;
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u = readl(GPIO_IO_CONF(ochip));
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if (input)
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u |= 1 << pin;
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else
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u &= ~(1 << pin);
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writel(u, GPIO_IO_CONF(ochip));
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}
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static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
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{
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u32 u;
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u = readl(GPIO_OUT(ochip));
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if (high)
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u |= 1 << pin;
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else
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u &= ~(1 << pin);
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writel(u, GPIO_OUT(ochip));
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}
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static inline void
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__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
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{
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u32 u;
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u = readl(GPIO_BLINK_EN(ochip));
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if (blink)
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u |= 1 << pin;
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else
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u &= ~(1 << pin);
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writel(u, GPIO_BLINK_EN(ochip));
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}
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static inline int
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orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
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{
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if (pin >= ochip->chip.ngpio)
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goto err_out;
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if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
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goto err_out;
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if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
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goto err_out;
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return 1;
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err_out:
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pr_debug("%s: invalid GPIO %d\n", __func__, pin);
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return false;
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}
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/*
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* GPIO primitives.
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*/
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static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
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orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
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return 0;
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return -EINVAL;
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}
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static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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unsigned long flags;
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if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
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return -EINVAL;
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spin_lock_irqsave(&ochip->lock, flags);
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__set_direction(ochip, pin, 1);
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spin_unlock_irqrestore(&ochip->lock, flags);
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return 0;
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}
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static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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int val;
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if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
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val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
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} else {
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val = readl(GPIO_OUT(ochip));
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}
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return (val >> pin) & 1;
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}
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static int
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orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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unsigned long flags;
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if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
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return -EINVAL;
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spin_lock_irqsave(&ochip->lock, flags);
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__set_blinking(ochip, pin, 0);
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__set_level(ochip, pin, value);
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__set_direction(ochip, pin, 0);
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spin_unlock_irqrestore(&ochip->lock, flags);
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return 0;
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}
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static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&ochip->lock, flags);
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__set_level(ochip, pin, value);
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spin_unlock_irqrestore(&ochip->lock, flags);
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}
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static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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return irq_create_mapping(ochip->domain,
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ochip->secondary_irq_base + pin);
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}
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/*
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* Orion-specific GPIO API extensions.
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*/
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static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
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{
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int i;
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for (i = 0; i < orion_gpio_chip_count; i++) {
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struct orion_gpio_chip *ochip = orion_gpio_chips + i;
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struct gpio_chip *chip = &ochip->chip;
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if (pin >= chip->base && pin < chip->base + chip->ngpio)
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return ochip;
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}
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return NULL;
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}
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void __init orion_gpio_set_unused(unsigned pin)
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{
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
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if (ochip == NULL)
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return;
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pin -= ochip->chip.base;
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/* Configure as output, drive low. */
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__set_level(ochip, pin, 0);
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__set_direction(ochip, pin, 0);
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}
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void __init orion_gpio_set_valid(unsigned pin, int mode)
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{
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
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if (ochip == NULL)
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return;
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pin -= ochip->chip.base;
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if (mode == 1)
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mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
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if (mode & GPIO_INPUT_OK)
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__set_bit(pin, &ochip->valid_input);
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else
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__clear_bit(pin, &ochip->valid_input);
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if (mode & GPIO_OUTPUT_OK)
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__set_bit(pin, &ochip->valid_output);
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else
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__clear_bit(pin, &ochip->valid_output);
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}
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void orion_gpio_set_blink(unsigned pin, int blink)
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{
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
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unsigned long flags;
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if (ochip == NULL)
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return;
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spin_lock_irqsave(&ochip->lock, flags);
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__set_level(ochip, pin & 31, 0);
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__set_blinking(ochip, pin & 31, blink);
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spin_unlock_irqrestore(&ochip->lock, flags);
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}
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EXPORT_SYMBOL(orion_gpio_set_blink);
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#define ORION_BLINK_HALF_PERIOD 100 /* ms */
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int orion_gpio_led_blink_set(unsigned gpio, int state,
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unsigned long *delay_on, unsigned long *delay_off)
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{
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if (delay_on && delay_off && !*delay_on && !*delay_off)
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*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
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switch (state) {
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case GPIO_LED_NO_BLINK_LOW:
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case GPIO_LED_NO_BLINK_HIGH:
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orion_gpio_set_blink(gpio, 0);
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gpio_set_value(gpio, state);
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break;
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case GPIO_LED_BLINK:
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orion_gpio_set_blink(gpio, 1);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
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/*****************************************************************************
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* Orion GPIO IRQ
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*
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static int gpio_irq_set_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct orion_gpio_chip *ochip = gc->private;
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int pin;
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u32 u;
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pin = d->hwirq - ochip->secondary_irq_base;
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u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
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if (!u) {
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return -EINVAL;
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}
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_NONE)
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return -EINVAL;
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/* Check if we need to change chip and handler */
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if (!(ct->type & type))
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if (irq_setup_alt_chip(d, type))
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return -EINVAL;
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/*
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* Configure interrupt polarity.
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*/
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
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u = readl(GPIO_IN_POL(ochip));
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u &= ~(1 << pin);
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writel(u, GPIO_IN_POL(ochip));
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} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
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u = readl(GPIO_IN_POL(ochip));
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u |= 1 << pin;
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writel(u, GPIO_IN_POL(ochip));
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} else if (type == IRQ_TYPE_EDGE_BOTH) {
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u32 v;
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v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
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/*
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* set initial polarity based on current input level
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*/
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u = readl(GPIO_IN_POL(ochip));
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if (v & (1 << pin))
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u |= 1 << pin; /* falling */
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else
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u &= ~(1 << pin); /* rising */
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writel(u, GPIO_IN_POL(ochip));
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}
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return 0;
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}
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static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct orion_gpio_chip *ochip = irq_get_handler_data(irq);
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u32 cause, type;
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int i;
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if (ochip == NULL)
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return;
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cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
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cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
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for (i = 0; i < ochip->chip.ngpio; i++) {
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int irq;
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irq = ochip->secondary_irq_base + i;
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if (!(cause & (1 << i)))
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continue;
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type = irq_get_trigger_type(irq);
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if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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/* Swap polarity (race with GPIO line) */
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u32 polarity;
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polarity = readl(GPIO_IN_POL(ochip));
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polarity ^= 1 << i;
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writel(polarity, GPIO_IN_POL(ochip));
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}
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generic_handle_irq(irq);
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}
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/seq_file.h>
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static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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struct orion_gpio_chip *ochip =
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container_of(chip, struct orion_gpio_chip, chip);
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u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
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int i;
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out = readl_relaxed(GPIO_OUT(ochip));
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io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
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blink = readl_relaxed(GPIO_BLINK_EN(ochip));
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in_pol = readl_relaxed(GPIO_IN_POL(ochip));
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data_in = readl_relaxed(GPIO_DATA_IN(ochip));
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cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
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edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
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lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
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for (i = 0; i < chip->ngpio; i++) {
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const char *label;
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u32 msk;
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bool is_out;
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label = gpiochip_is_requested(chip, i);
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if (!label)
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continue;
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msk = 1 << i;
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is_out = !(io_conf & msk);
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seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
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if (is_out) {
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seq_printf(s, " out %s %s\n",
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out & msk ? "hi" : "lo",
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blink & msk ? "(blink )" : "");
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continue;
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}
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seq_printf(s, " in %s (act %s) - IRQ",
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(data_in ^ in_pol) & msk ? "hi" : "lo",
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in_pol & msk ? "lo" : "hi");
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if (!((edg_msk | lvl_msk) & msk)) {
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seq_printf(s, " disabled\n");
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continue;
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}
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if (edg_msk & msk)
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seq_printf(s, " edge ");
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if (lvl_msk & msk)
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seq_printf(s, " level");
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seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
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}
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}
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#else
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#define orion_gpio_dbg_show NULL
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#endif
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void __init orion_gpio_init(struct device_node *np,
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int gpio_base, int ngpio,
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void __iomem *base, int mask_offset,
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int secondary_irq_base,
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int irqs[4])
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{
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struct orion_gpio_chip *ochip;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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char gc_label[16];
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int i;
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if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
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return;
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snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
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orion_gpio_chip_count);
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ochip = orion_gpio_chips + orion_gpio_chip_count;
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ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
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ochip->chip.request = orion_gpio_request;
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ochip->chip.direction_input = orion_gpio_direction_input;
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ochip->chip.get = orion_gpio_get;
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ochip->chip.direction_output = orion_gpio_direction_output;
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ochip->chip.set = orion_gpio_set;
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ochip->chip.to_irq = orion_gpio_to_irq;
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ochip->chip.base = gpio_base;
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ochip->chip.ngpio = ngpio;
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ochip->chip.can_sleep = 0;
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#ifdef CONFIG_OF
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ochip->chip.of_node = np;
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#endif
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ochip->chip.dbg_show = orion_gpio_dbg_show;
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spin_lock_init(&ochip->lock);
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ochip->base = (void __iomem *)base;
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ochip->valid_input = 0;
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ochip->valid_output = 0;
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ochip->mask_offset = mask_offset;
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ochip->secondary_irq_base = secondary_irq_base;
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gpiochip_add(&ochip->chip);
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/*
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* Mask and clear GPIO interrupts.
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*/
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writel(0, GPIO_EDGE_CAUSE(ochip));
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writel(0, GPIO_EDGE_MASK(ochip));
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writel(0, GPIO_LEVEL_MASK(ochip));
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/* Setup the interrupt handlers. Each chip can have up to 4
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* interrupt handlers, with each handler dealing with 8 GPIO
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* pins. */
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for (i = 0; i < 4; i++) {
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if (irqs[i]) {
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irq_set_handler_data(irqs[i], ochip);
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irq_set_chained_handler(irqs[i], gpio_irq_handler);
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}
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}
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gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
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secondary_irq_base,
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ochip->base, handle_level_irq);
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gc->private = ochip;
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ct = gc->chip_types;
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ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct->chip.name = ochip->chip.label;
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ct++;
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ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
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ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
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ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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ct->chip.irq_ack = irq_gc_ack_clr_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct->handler = handle_edge_irq;
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ct->chip.name = ochip->chip.label;
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|
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irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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|
|
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/* Setup irq domain on top of the generic chip. */
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ochip->domain = irq_domain_add_legacy(np,
|
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ochip->chip.ngpio,
|
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ochip->secondary_irq_base,
|
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ochip->secondary_irq_base,
|
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&irq_domain_simple_ops,
|
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ochip);
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if (!ochip->domain)
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panic("%s: couldn't allocate irq domain (DT).\n",
|
|
ochip->chip.label);
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|
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orion_gpio_chip_count++;
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}
|
|
|
|
#ifdef CONFIG_OF
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static void __init orion_gpio_of_init_one(struct device_node *np,
|
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int irq_gpio_base)
|
|
{
|
|
int ngpio, gpio_base, mask_offset;
|
|
void __iomem *base;
|
|
int ret, i;
|
|
int irqs[4];
|
|
int secondary_irq_base;
|
|
|
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ret = of_property_read_u32(np, "ngpio", &ngpio);
|
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if (ret)
|
|
goto out;
|
|
ret = of_property_read_u32(np, "mask-offset", &mask_offset);
|
|
if (ret == -EINVAL)
|
|
mask_offset = 0;
|
|
else
|
|
goto out;
|
|
base = of_iomap(np, 0);
|
|
if (!base)
|
|
goto out;
|
|
|
|
secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count);
|
|
gpio_base = 32 * orion_gpio_chip_count;
|
|
|
|
/* Get the interrupt numbers. Each chip can have up to 4
|
|
* interrupt handlers, with each handler dealing with 8 GPIO
|
|
* pins. */
|
|
|
|
for (i = 0; i < 4; i++)
|
|
irqs[i] = irq_of_parse_and_map(np, i);
|
|
|
|
orion_gpio_init(np, gpio_base, ngpio, base, mask_offset,
|
|
secondary_irq_base, irqs);
|
|
return;
|
|
out:
|
|
pr_err("%s: %s: missing mandatory property\n", __func__, np->name);
|
|
}
|
|
|
|
void __init orion_gpio_of_init(int irq_gpio_base)
|
|
{
|
|
struct device_node *np;
|
|
|
|
for_each_compatible_node(np, NULL, "marvell,orion-gpio")
|
|
orion_gpio_of_init_one(np, irq_gpio_base);
|
|
}
|
|
#endif
|