linux_dsm_epyc7002/drivers/clk/sunxi-ng
Andre Przywara d99d58b8df clk: sunxi-ng: h6: Fix clock divider range on some clocks
[ Upstream commit 04ef679591c76571a9e7d5ca48316cc86fa0ef12 ]

While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.

By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.

Change to number of bits in the affected clock's description.

Fixes: 524353ea48 ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@arm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-03-04 11:37:58 +01:00
..
ccu_common.c
ccu_common.h
ccu_div.c
ccu_div.h
ccu_frac.c
ccu_frac.h
ccu_gate.c
ccu_gate.h
ccu_mmc_timing.c
ccu_mp.c clk: sunxi-ng: mp: fix parent rate change flag check 2021-02-17 11:02:28 +01:00
ccu_mp.h
ccu_mult.c
ccu_mult.h
ccu_mux.c
ccu_mux.h
ccu_nk.c
ccu_nk.h
ccu_nkm.c
ccu_nkm.h
ccu_nkmp.c
ccu_nkmp.h
ccu_nm.c
ccu_nm.h
ccu_phase.c
ccu_phase.h
ccu_reset.c
ccu_reset.h
ccu_sdm.c
ccu_sdm.h
ccu-sun4i-a10.c
ccu-sun4i-a10.h
ccu-sun5i.c
ccu-sun5i.h
ccu-sun6i-a31.c
ccu-sun6i-a31.h clk: sunxi: a31: Export the MIPI PLL 2020-01-04 09:45:09 +01:00
ccu-sun8i-a23-a33.h clk: sunxi: a23/a33: Export the MIPI PLL 2020-01-04 09:45:19 +01:00
ccu-sun8i-a23.c
ccu-sun8i-a33.c
ccu-sun8i-a83t.c
ccu-sun8i-a83t.h
ccu-sun8i-de2.c clk: sunxi-ng: sun8i-de2: Sort structures 2020-02-12 19:01:16 +01:00
ccu-sun8i-de2.h
ccu-sun8i-h3.c clk: sunxi-ng: Make sure divider tables have sentinel 2020-12-30 11:54:01 +01:00
ccu-sun8i-h3.h
ccu-sun8i-r40.c clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL 2020-08-25 16:42:55 +02:00
ccu-sun8i-r40.h clk: sunxi-ng: r40: Export MBUS clock 2020-01-03 10:37:14 +01:00
ccu-sun8i-r.c clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock 2020-01-02 10:27:47 +01:00
ccu-sun8i-r.h
ccu-sun8i-v3s.c clk: sunxi-ng: v3s: Fix incorrect number of hw_clks. 2019-12-09 08:49:31 +01:00
ccu-sun8i-v3s.h clk: sunxi-ng: v3s: Fix incorrect number of hw_clks. 2019-12-09 08:49:31 +01:00
ccu-sun9i-a80-de.c
ccu-sun9i-a80-de.h
ccu-sun9i-a80-usb.c
ccu-sun9i-a80-usb.h
ccu-sun9i-a80.c
ccu-sun9i-a80.h
ccu-sun50i-a64.c clk: sunxi-ng: Make sure divider tables have sentinel 2020-12-30 11:54:01 +01:00
ccu-sun50i-a64.h clk: sunxi-ng: a64: Export MBUS clock 2020-02-11 07:49:14 +01:00
ccu-sun50i-a100-r.c clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00
ccu-sun50i-a100-r.h clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00
ccu-sun50i-a100.c clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00
ccu-sun50i-a100.h clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00
ccu-sun50i-h6-r.c clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order 2020-01-02 10:28:47 +01:00
ccu-sun50i-h6-r.h
ccu-sun50i-h6.c clk: sunxi-ng: h6: Fix clock divider range on some clocks 2021-03-04 11:37:58 +01:00
ccu-sun50i-h6.h
ccu-suniv-f1c100s.c
ccu-suniv-f1c100s.h
Kconfig clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00
Makefile clk: sunxi-ng: add support for the Allwinner A100 CCU 2020-08-25 10:52:18 +02:00