Dinh Nguyen e92bd19246 clk: agilex/stratix10: fix bypass representation ... commit 6855ee839699bdabb4b16cf942557fd763bcb1fa upstream. Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp, emac0/1/2) have a bypass setting that can use the boot_clk. The previous representation was not correct. Fix the representation. Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-07-14 16:55:44 +02:00
..
clk-agilex.c	clk: agilex/stratix10: fix bypass representation	2021-07-14 16:55:44 +02:00
clk-gate-a10.c
clk-gate-s10.c
clk-gate.c
clk-periph-a10.c
clk-periph-s10.c
clk-periph.c
clk-pll-a10.c
clk-pll-s10.c
clk-pll.c
clk-s10.c	clk: agilex/stratix10: fix bypass representation	2021-07-14 16:55:44 +02:00
clk.c
clk.h
Makefile
stratix10-clk.h