mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:34:43 +07:00
658fd65cf0
It is not allowed to sleep to early in the boot process and this may lead
to kernel issues if the bootloader didn't prepare the slow clock and main
clock.
This results in the following error and dump stack on the AriettaG25:
bad: scheduling from the idle thread!
Ensure it is possible to sleep, else simply have a delay.
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20190920153906.20887-1-alexandre.belloni@bootlin.com
Fixes: 80eded6ce8 ("clk: at91: add slow clks driver")
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
513 lines
11 KiB
C
513 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define SLOW_CLOCK_FREQ 32768
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#define MAINF_DIV 16
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#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
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SLOW_CLOCK_FREQ)
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#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
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#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
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#define MOR_KEY_MASK (0xff << 16)
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#define clk_main_parent_select(s) (((s) & \
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(AT91_PMC_MOSCEN | \
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AT91_PMC_OSCBYPASS)) ? 1 : 0)
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struct clk_main_osc {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
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struct clk_main_rc_osc {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned long frequency;
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unsigned long accuracy;
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};
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#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
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struct clk_rm9200_main {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
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struct clk_sam9x5_main {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 parent;
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};
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#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
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static inline bool clk_main_osc_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_MOSCS;
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}
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static int clk_main_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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tmp &= ~MOR_KEY_MASK;
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if (tmp & AT91_PMC_OSCBYPASS)
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return 0;
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if (!(tmp & AT91_PMC_MOSCEN)) {
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tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
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regmap_write(regmap, AT91_CKGR_MOR, tmp);
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}
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while (!clk_main_osc_ready(regmap))
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cpu_relax();
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return 0;
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}
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static void clk_main_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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if (tmp & AT91_PMC_OSCBYPASS)
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return;
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if (!(tmp & AT91_PMC_MOSCEN))
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return;
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tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
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regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
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}
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static int clk_main_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_main_osc *osc = to_clk_main_osc(hw);
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struct regmap *regmap = osc->regmap;
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u32 tmp, status;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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if (tmp & AT91_PMC_OSCBYPASS)
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return 1;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
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}
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static const struct clk_ops main_osc_ops = {
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.prepare = clk_main_osc_prepare,
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.unprepare = clk_main_osc_unprepare,
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.is_prepared = clk_main_osc_is_prepared,
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};
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struct clk_hw * __init
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at91_clk_register_main_osc(struct regmap *regmap,
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const char *name,
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const char *parent_name,
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bool bypass)
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{
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struct clk_main_osc *osc;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !parent_name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->regmap = regmap;
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if (bypass)
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regmap_update_bits(regmap,
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AT91_CKGR_MOR, MOR_KEY_MASK |
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AT91_PMC_OSCBYPASS,
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AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static bool clk_main_rc_osc_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_MOSCRCS;
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}
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static int clk_main_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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if (!(mor & AT91_PMC_MOSCRCEN))
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regmap_update_bits(regmap, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
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AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
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while (!clk_main_rc_osc_ready(regmap))
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cpu_relax();
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return 0;
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}
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static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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if (!(mor & AT91_PMC_MOSCRCEN))
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return;
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regmap_update_bits(regmap, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
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}
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static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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struct regmap *regmap = osc->regmap;
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unsigned int mor, status;
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regmap_read(regmap, AT91_CKGR_MOR, &mor);
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regmap_read(regmap, AT91_PMC_SR, &status);
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return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
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}
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static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
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return osc->accuracy;
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}
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static const struct clk_ops main_rc_osc_ops = {
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.prepare = clk_main_rc_osc_prepare,
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.unprepare = clk_main_rc_osc_unprepare,
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.is_prepared = clk_main_rc_osc_is_prepared,
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.recalc_rate = clk_main_rc_osc_recalc_rate,
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.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
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};
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struct clk_hw * __init
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at91_clk_register_main_rc_osc(struct regmap *regmap,
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const char *name,
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u32 frequency, u32 accuracy)
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{
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struct clk_main_rc_osc *osc;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name || !frequency)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &main_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->regmap = regmap;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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hw = &osc->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(osc);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static int clk_main_probe_frequency(struct regmap *regmap)
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{
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unsigned long prep_time, timeout;
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unsigned int mcfr;
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timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
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do {
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prep_time = jiffies;
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regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
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if (mcfr & AT91_PMC_MAINRDY)
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return 0;
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if (system_state < SYSTEM_RUNNING)
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udelay(MAINF_LOOP_MIN_WAIT);
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else
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usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
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} while (time_before(prep_time, timeout));
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return -ETIMEDOUT;
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}
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static unsigned long clk_main_recalc_rate(struct regmap *regmap,
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unsigned long parent_rate)
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{
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unsigned int mcfr;
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if (parent_rate)
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return parent_rate;
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pr_warn("Main crystal frequency not set, using approximate value\n");
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regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
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if (!(mcfr & AT91_PMC_MAINRDY))
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return 0;
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return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
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}
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static int clk_rm9200_main_prepare(struct clk_hw *hw)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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return clk_main_probe_frequency(clkmain->regmap);
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}
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static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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unsigned int status;
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regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
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return status & AT91_PMC_MAINRDY ? 1 : 0;
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}
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static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
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return clk_main_recalc_rate(clkmain->regmap, parent_rate);
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}
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static const struct clk_ops rm9200_main_ops = {
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.prepare = clk_rm9200_main_prepare,
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.is_prepared = clk_rm9200_main_is_prepared,
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.recalc_rate = clk_rm9200_main_recalc_rate,
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};
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struct clk_hw * __init
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at91_clk_register_rm9200_main(struct regmap *regmap,
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const char *name,
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const char *parent_name)
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{
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struct clk_rm9200_main *clkmain;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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if (!name)
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return ERR_PTR(-EINVAL);
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if (!parent_name)
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return ERR_PTR(-EINVAL);
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clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
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if (!clkmain)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &rm9200_main_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = 0;
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clkmain->hw.init = &init;
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clkmain->regmap = regmap;
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hw = &clkmain->hw;
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ret = clk_hw_register(NULL, &clkmain->hw);
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if (ret) {
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kfree(clkmain);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_MOSCSELS ? 1 : 0;
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}
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static int clk_sam9x5_main_prepare(struct clk_hw *hw)
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{
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struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
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struct regmap *regmap = clkmain->regmap;
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while (!clk_sam9x5_main_ready(regmap))
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cpu_relax();
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return clk_main_probe_frequency(regmap);
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}
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static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
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{
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struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
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return clk_sam9x5_main_ready(clkmain->regmap);
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}
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static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
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return clk_main_recalc_rate(clkmain->regmap, parent_rate);
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}
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static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
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struct regmap *regmap = clkmain->regmap;
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unsigned int tmp;
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if (index > 1)
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return -EINVAL;
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regmap_read(regmap, AT91_CKGR_MOR, &tmp);
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tmp &= ~MOR_KEY_MASK;
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if (index && !(tmp & AT91_PMC_MOSCSEL))
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regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
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else if (!index && (tmp & AT91_PMC_MOSCSEL))
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regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
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while (!clk_sam9x5_main_ready(regmap))
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cpu_relax();
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return 0;
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}
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static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
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unsigned int status;
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regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
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return clk_main_parent_select(status);
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}
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static const struct clk_ops sam9x5_main_ops = {
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.prepare = clk_sam9x5_main_prepare,
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.is_prepared = clk_sam9x5_main_is_prepared,
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.recalc_rate = clk_sam9x5_main_recalc_rate,
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.set_parent = clk_sam9x5_main_set_parent,
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.get_parent = clk_sam9x5_main_get_parent,
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};
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struct clk_hw * __init
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at91_clk_register_sam9x5_main(struct regmap *regmap,
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const char *name,
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const char **parent_names,
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int num_parents)
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{
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struct clk_sam9x5_main *clkmain;
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struct clk_init_data init;
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unsigned int status;
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struct clk_hw *hw;
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int ret;
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if (!name)
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return ERR_PTR(-EINVAL);
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if (!parent_names || !num_parents)
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return ERR_PTR(-EINVAL);
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clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
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if (!clkmain)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9x5_main_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = CLK_SET_PARENT_GATE;
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clkmain->hw.init = &init;
|
|
clkmain->regmap = regmap;
|
|
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
|
|
clkmain->parent = clk_main_parent_select(status);
|
|
|
|
hw = &clkmain->hw;
|
|
ret = clk_hw_register(NULL, &clkmain->hw);
|
|
if (ret) {
|
|
kfree(clkmain);
|
|
hw = ERR_PTR(ret);
|
|
}
|
|
|
|
return hw;
|
|
}
|