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db0dbd57d5
While synchronization, count register will go backwards for the master.
If synchronise_count_master() runs before synchronise_count_slave(),
skew becomes even more. The skew is very harmful for CPU hotplug (CPU0
do synchronization with CPU1, then CPU0 do synchronization with CPU2
and CPU0's count goes backwards, so it will be out of sync with CPU1).
After the commit cf9bfe55f2 (MIPS: Synchronize MIPS count one
CPU at a time), we needn't evaluate count_reference at the beginning of
synchronise_count_master() any more. Thus, we evaluate the initcount (It
seems like count_reference is redundant) in the 2nd loop. Since we write
the count register in the last loop, we don't need additional barriers
(the existing memory barriers are enough).
Moreover, I think we loop 3 times is enough to get a primed instruction
cache, this can also get less skew than looping 5 times.
Comments are also updated in this patch.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/12163/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/*
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* Count register synchronisation.
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*
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* All CPUs will have their count registers synchronised to the CPU0 next time
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* value. This can cause a small timewarp for CPU0. All other CPU's should
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* not have done anything significant (but they may have had interrupts
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* enabled briefly - prom_smp_finish() should not be responsible for enabling
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* interrupts...)
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*/
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#include <linux/kernel.h>
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#include <linux/irqflags.h>
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#include <linux/cpumask.h>
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#include <asm/r4k-timer.h>
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#include <linux/atomic.h>
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#include <asm/barrier.h>
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#include <asm/mipsregs.h>
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static unsigned int initcount = 0;
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static atomic_t count_count_start = ATOMIC_INIT(0);
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static atomic_t count_count_stop = ATOMIC_INIT(0);
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#define COUNTON 100
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#define NR_LOOPS 3
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void synchronise_count_master(int cpu)
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{
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int i;
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unsigned long flags;
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printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
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local_irq_save(flags);
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/*
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* We loop a few times to get a primed instruction cache,
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* then the last pass is more or less synchronised and
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* the master and slaves each set their cycle counters to a known
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* value all at once. This reduces the chance of having random offsets
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* between the processors, and guarantees that the maximum
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* delay between the cycle counters is never bigger than
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* the latency of information-passing (cachelines) between
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* two CPUs.
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*/
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for (i = 0; i < NR_LOOPS; i++) {
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/* slaves loop on '!= 2' */
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while (atomic_read(&count_count_start) != 1)
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mb();
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atomic_set(&count_count_stop, 0);
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smp_wmb();
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/* Let the slave writes its count register */
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atomic_inc(&count_count_start);
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/* Count will be initialised to current timer */
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if (i == 1)
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initcount = read_c0_count();
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/*
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* Everyone initialises count in the last loop:
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*/
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if (i == NR_LOOPS-1)
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write_c0_count(initcount);
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/*
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* Wait for slave to leave the synchronization point:
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*/
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while (atomic_read(&count_count_stop) != 1)
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mb();
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atomic_set(&count_count_start, 0);
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smp_wmb();
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atomic_inc(&count_count_stop);
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}
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/* Arrange for an interrupt in a short while */
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write_c0_compare(read_c0_count() + COUNTON);
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local_irq_restore(flags);
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/*
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* i386 code reported the skew here, but the
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* count registers were almost certainly out of sync
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* so no point in alarming people
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*/
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printk("done.\n");
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}
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void synchronise_count_slave(int cpu)
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{
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int i;
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/*
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* Not every cpu is online at the time this gets called,
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* so we first wait for the master to say everyone is ready
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*/
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for (i = 0; i < NR_LOOPS; i++) {
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atomic_inc(&count_count_start);
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while (atomic_read(&count_count_start) != 2)
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mb();
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/*
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* Everyone initialises count in the last loop:
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*/
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if (i == NR_LOOPS-1)
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write_c0_count(initcount);
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atomic_inc(&count_count_stop);
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while (atomic_read(&count_count_stop) != 2)
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mb();
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}
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/* Arrange for an interrupt in a short while */
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write_c0_compare(read_c0_count() + COUNTON);
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}
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#undef NR_LOOPS
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