Greg Kroah-Hartman daf273350d phy: for 4.5 ... *) new PHY driver for hi6220 usb and rcar gen3 usb2 *) deprecate phy-omap-control driver. phy-omap-control driver was added when there was no proper infrastructure for doing control module initialization. The phy-omap-control driver is not an 'actual' PHY driver and it was just a hack to do PHY related control module initialization. Now with SYSCON framework in the kernel, control module setttings can be done using APIs provided by syscon. *) usbphy-internal pll creates the needed 480MHz and is also a supply-clock back to the core clock-controller in Rockchip SoCs. This is now modeled as a real clock. *) calibrate mt65xx usb3 PHY for better eye diagram and receiver sensitivity. *) Miscellaneous cleanups. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJWeR+CAAoJEA5ceFyATYLZG8QP/jlux4ejRKhaO/BYd2gSEOij H6CO+3O+oQqgKHdDvgGrE5vAqRfxBZI9UErOEBUcPOY+Qdp0s5Wg657WuJR1sSDK iNwho1AS2ZuQHqxVDaDToBCTIwliDVkT0+eIgq5tGZaHBh0/iOUEzjnODcaR36a/ VFPPTTFmkeX9Y0qzyWx/eVASBNguKo6/8/h9PV0zIFkunaE28rDvR2F9x4QSfBaV 737iivHmVxe+/dQ3EwLymrVu1LMwporEqctWUFzUVHsSZfJH7lCErzCs5qPNCoOw OqqHJXmk+FtYix3GMj+sGSD3qR83ml031EeCxpmHQ4OVNfTTIodF/po9K9NRkM8K 4rA9EkV5xjgWZFw/38ANvozcUXDbVOKMqhwMAH8hLWvIDzO4HfPY/hpRpXzTc+vo c7QowH+SP/8lXWGEVvFNjDWaowC7ajkAq94RFXQLTucySP9jgaDDD9nK2onMPD2S Z2t7QXgdu9zuLziWeigriSIsjQIJ7gCfAHpUAaeX9VDocgzTqOoweYFTQuU89S9S FrfE/B3k+ZI+RDwvsbAShzmMxoYSpct5fhwjA+6D0L1v7piU0GSAT5wMGYFumC32 BQWi41I2o5ory3rOOfzFa5GUxBEG8dJNjIgJKvcMT/2QH0zinY6c03a1wN+V7iRV i1YqBUUvHCEnbsNHrxmN =Bu7H -----END PGP SIGNATURE----- Merge tag 'phy-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.5 *) new PHY driver for hi6220 usb and rcar gen3 usb2 *) deprecate phy-omap-control driver. phy-omap-control driver was added when there was no proper infrastructure for doing control module initialization. The phy-omap-control driver is not an 'actual' PHY driver and it was just a hack to do PHY related control module initialization. Now with SYSCON framework in the kernel, control module setttings can be done using APIs provided by syscon. *) usbphy-internal pll creates the needed 480MHz and is also a supply-clock back to the core clock-controller in Rockchip SoCs. This is now modeled as a real clock. *) calibrate mt65xx usb3 PHY for better eye diagram and receiver sensitivity. *) Miscellaneous cleanups. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>		2015-12-26 17:01:18 -08:00
..
bindings	phy: for 4.5	2015-12-26 17:01:18 -08:00
00-INDEX
booting-without-of.txt	ARM: 8354/1: Documentation: devicetree: root node serial-number property documentation	2015-05-08 10:42:34 +01:00
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt	Documentation: rename of_selftest.txt to of_unittest.txt	2015-03-25 00:50:53 -05:00
overlay-notes.txt	Documentation: devicetree: Fix double words in Doumentation/devicetree	2015-01-28 15:13:11 -07:00
todo.txt
usage-model.txt