Eugeniy Paltsev daeeb438c0 ARC: clk: introduce HSDK pll driver ... HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-08-30 22:36:05 -07:00
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bindings	ARC: clk: introduce HSDK pll driver	2017-08-30 22:36:05 -07:00
00-INDEX
booting-without-of.txt	of: update ePAPR references to point to Devicetree Specification	2017-06-22 11:22:06 -05:00
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt
overlay-notes.txt	Documentation: remove overlay-notes reference to non-existent file	2017-06-22 11:14:01 -05:00
todo.txt
usage-model.txt	of: update ePAPR references to point to Devicetree Specification	2017-06-22 11:22:06 -05:00