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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c65ec13596
the 'soc' node in the common .dtsi for MPC5121 has an '#interrupt-cells' property although this node is not an interrupt controller remove this erroneously placed property because starting with v3.13-rc1 lookup and resolution of 'interrupts' specs for peripherals gets misled, emits 'no irq domain found' WARN() messages and breaks the boot process irq: no irq domain found for /soc@80000000 ! ------------[ cut here ]------------ WARNING: at drivers/of/platform.c:171 Modules linked in: CPU: 0 PID: 1 Comm: swapper Tainted: G W 3.13.0-rc1-00001-g8a66234 #8 task: df823bb0 ti: df834000 task.ti: df834000 NIP: c02b5190 LR: c02b5180 CTR: c01cf4e0 REGS: df835c50 TRAP: 0700 Tainted: G W (3.13.0-rc1-00001-g8a66234) MSR: 00029032 <EE,ME,IR,DR,RI> CR: 229a9d42 XER: 20000000 GPR00: c02b5180 df835d00 df823bb0 00000000 00000000 df835b18 ffffffff 00000308 GPR08: c0479cc0 c0480000 c0479cc0 00000308 00000308 00000000 c00040fc 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 df850880 GPR24: df84d670 00000000 00000001df8561a0dffffccc df85089c 00000020 00000001 NIP [c02b5190] of_device_alloc+0xf4/0x1a0 LR [c02b5180] of_device_alloc+0xe4/0x1a0 Call Trace: [df835d00] [c02b5180] of_device_alloc+0xe4/0x1a0 (unreliable) [df835d50] [c02b5278] of_platform_device_create_pdata+0x3c/0xc8 [df835d70] [c02b53fc] of_platform_bus_create+0xf8/0x170 [df835dc0] [c02b5448] of_platform_bus_create+0x144/0x170 [df835e10] [c02b55a8] of_platform_bus_probe+0x98/0xe8 [df835e30] [c0437508] mpc512x_init+0x28/0x1c4 [df835e70] [c0435de8] ppc_init+0x4c/0x60 [df835e80] [c0003b28] do_one_initcall+0x150/0x1a4 [df835ef0] [c0432048] kernel_init_freeable+0x114/0x1c0 [df835f30] [c0004114] kernel_init+0x18/0x124 [df835f40] [c000e910] ret_from_kernel_thread+0x5c/0x64 Instruction dump: 409effd4 57c9103a 57de2834 7c89f050 7f83e378 7c972214 7f45d378 48001f55 7c63d278 7c630034 5463d97e 687a0001 <0f1a0000> 2f990000 387b0010 939b0098 ---[ end trace 2257f10e5a20cbdd ]--- ... irq: no irq domain found for /soc@80000000 ! fsl-diu-fb 80002100.display: could not get DIU IRQ fsl-diu-fb: probe of 80002100.display failed with error -22 irq: no irq domain found for /soc@80000000 ! mpc512x_dma 80014000.dma: Error mapping IRQ! mpc512x_dma: probe of 80014000.dma failed with error -22 ... irq: no irq domain found for /soc@80000000 ! fs_enet: probe of 80002800.ethernet failed with error -22 ... irq: no irq domain found for /soc@80000000 ! mpc5121-rtc 80000a00.rtc: mpc5121_rtc_probe: could not request irq: 0 mpc5121-rtc: probe of 80000a00.rtc failed with error -22 ... Cc: Anatolij Gustschin <agust@denx.de> Cc: linuxppc-dev@lists.ozlabs.org Cc: devicetree@vger.kernel.org Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
412 lines
8.4 KiB
Plaintext
412 lines
8.4 KiB
Plaintext
/*
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* base MPC5121 Device Tree Source
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*
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* Copyright 2007-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "mpc5121";
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compatible = "fsl,mpc5121";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&ipic>;
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aliases {
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ethernet0 = ð0;
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pci = &pci;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5121@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; /* 32 bytes */
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i-cache-line-size = <0x20>; /* 32 bytes */
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d-cache-size = <0x8000>; /* L1, 32K */
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i-cache-size = <0x8000>; /* L1, 32K */
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timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
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bus-frequency = <198000000>; /* 198 MHz csb bus */
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clock-frequency = <396000000>; /* 396 MHz ppc core */
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256MB at 0 */
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};
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mbx@20000000 {
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compatible = "fsl,mpc5121-mbx";
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reg = <0x20000000 0x4000>;
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interrupts = <66 0x8>;
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};
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sram@30000000 {
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compatible = "fsl,mpc5121-sram";
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reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
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};
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nfc@40000000 {
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compatible = "fsl,mpc5121-nfc";
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reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
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interrupts = <6 8>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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localbus@80000020 {
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compatible = "fsl,mpc5121-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x80000020 0x40>;
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interrupts = <7 0x8>;
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ranges = <0x0 0x0 0xfc000000 0x04000000>;
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};
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soc@80000000 {
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compatible = "fsl,mpc5121-immr";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000000 0x400000>;
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reg = <0x80000000 0x400000>;
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bus-frequency = <66000000>; /* 66 MHz ips bus */
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/*
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* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@c00 {
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compatible = "fsl,mpc5121-ipic", "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0xc00 0x100>;
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};
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/* Watchdog timer */
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wdt@900 {
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compatible = "fsl,mpc5121-wdt";
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reg = <0x900 0x100>;
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};
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/* Real time clock */
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rtc@a00 {
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compatible = "fsl,mpc5121-rtc";
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reg = <0xa00 0x100>;
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interrupts = <79 0x8 80 0x8>;
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};
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/* Reset module */
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reset@e00 {
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compatible = "fsl,mpc5121-reset";
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reg = <0xe00 0x100>;
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};
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/* Clock control */
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clock@f00 {
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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};
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/* Power Management Controller */
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pmc@1000{
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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interrupts = <83 0x8>;
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};
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gpio@1100 {
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compatible = "fsl,mpc5121-gpio";
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reg = <0x1100 0x100>;
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interrupts = <78 0x8>;
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};
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can@1300 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x1300 0x80>;
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interrupts = <12 0x8>;
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};
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can@1380 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x1380 0x80>;
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interrupts = <13 0x8>;
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};
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sdhc@1500 {
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compatible = "fsl,mpc5121-sdhc";
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reg = <0x1500 0x100>;
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interrupts = <8 0x8>;
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dmas = <&dma0 30>;
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dma-names = "rx-tx";
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};
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i2c@1700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1700 0x20>;
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interrupts = <9 0x8>;
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};
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i2c@1720 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1720 0x20>;
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interrupts = <10 0x8>;
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};
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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};
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i2ccontrol@1760 {
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compatible = "fsl,mpc5121-i2c-ctrl";
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reg = <0x1760 0x8>;
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};
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axe@2000 {
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compatible = "fsl,mpc5121-axe";
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reg = <0x2000 0x100>;
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interrupts = <42 0x8>;
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};
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display@2100 {
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compatible = "fsl,mpc5121-diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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};
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can@2300 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x2300 0x80>;
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interrupts = <90 0x8>;
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};
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can@2380 {
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compatible = "fsl,mpc5121-mscan";
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reg = <0x2380 0x80>;
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interrupts = <91 0x8>;
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};
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viu@2400 {
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compatible = "fsl,mpc5121-viu";
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reg = <0x2400 0x400>;
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interrupts = <67 0x8>;
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};
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mdio@2800 {
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compatible = "fsl,mpc5121-fec-mdio";
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reg = <0x2800 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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eth0: ethernet@2800 {
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device_type = "network";
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compatible = "fsl,mpc5121-fec";
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reg = <0x2800 0x800>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <4 0x8>;
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};
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/* USB1 using external ULPI PHY */
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usb@3000 {
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x3000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <43 0x8>;
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dr_mode = "otg";
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phy_type = "ulpi";
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};
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/* USB0 using internal UTMI PHY */
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usb@4000 {
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x4000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <44 0x8>;
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dr_mode = "otg";
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phy_type = "utmi_wide";
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};
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/* IO control */
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ioctl@a000 {
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compatible = "fsl,mpc5121-ioctl";
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reg = <0xA000 0x1000>;
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};
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/* LocalPlus controller */
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lpc@10000 {
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compatible = "fsl,mpc5121-lpc";
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reg = <0x10000 0x200>;
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};
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pata@10200 {
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compatible = "fsl,mpc5121-pata";
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reg = <0x10200 0x100>;
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interrupts = <5 0x8>;
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};
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/* 512x PSCs are not 52xx PSC compatible */
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/* PSC0 */
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psc@11000 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11000 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC1 */
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psc@11100 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11100 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC2 */
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psc@11200 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11200 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC3 */
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psc@11300 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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reg = <0x11300 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC4 */
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psc@11400 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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reg = <0x11400 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC5 */
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psc@11500 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11500 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC6 */
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psc@11600 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11600 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC7 */
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psc@11700 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11700 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC8 */
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psc@11800 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11800 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC9 */
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psc@11900 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11900 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC10 */
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psc@11a00 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11a00 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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/* PSC11 */
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psc@11b00 {
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compatible = "fsl,mpc5121-psc";
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reg = <0x11b00 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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pscfifo@11f00 {
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compatible = "fsl,mpc5121-psc-fifo";
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reg = <0x11f00 0x100>;
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interrupts = <40 0x8>;
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};
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dma0: dma@14000 {
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compatible = "fsl,mpc5121-dma";
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reg = <0x14000 0x1800>;
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interrupts = <65 0x8>;
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};
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};
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pci: pci@80008500 {
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compatible = "fsl,mpc5121-pci";
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device_type = "pci";
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interrupts = <1 0x8>;
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clock-frequency = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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reg = <0x80008500 0x100 /* internal registers */
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0x80008300 0x8>; /* config space access registers */
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bus-range = <0x0 0x0>;
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ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
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};
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};
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