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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
a2ca85ad72
Aggregation will wait for next packet until limit aggr size/number reach. Packet might be drop and also packet dequeue will be stop in some cases. This patch add timer to flush packets in aggregation list to avoid long time waiting. Signed-off-by: Xinming Hu <huxm@marvell.com> Signed-off-by: Cathy Luo <cluo@marvell.com> Signed-off-by: Ganapathi Bhat <gbhat@marvell.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/*
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* This file contains definitions for mwifiex USB interface driver.
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*
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* Copyright (C) 2012-2014, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_USB_H
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#define _MWIFIEX_USB_H
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#include <linux/completion.h>
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#include <linux/usb.h>
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#define USB8XXX_VID 0x1286
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#define USB8766_PID_1 0x2041
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#define USB8766_PID_2 0x2042
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#define USB8797_PID_1 0x2043
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#define USB8797_PID_2 0x2044
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#define USB8801_PID_1 0x2049
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#define USB8801_PID_2 0x204a
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#define USB8997_PID_1 0x2052
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#define USB8997_PID_2 0x204e
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#define USB8XXX_FW_DNLD 1
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#define USB8XXX_FW_READY 2
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#define USB8XXX_FW_MAX_RETRY 3
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#define MWIFIEX_TX_DATA_PORT 2
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#define MWIFIEX_TX_DATA_URB 6
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#define MWIFIEX_RX_DATA_URB 6
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#define MWIFIEX_USB_TIMEOUT 100
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#define USB8766_DEFAULT_FW_NAME "mrvl/usb8766_uapsta.bin"
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#define USB8797_DEFAULT_FW_NAME "mrvl/usb8797_uapsta.bin"
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#define USB8801_DEFAULT_FW_NAME "mrvl/usb8801_uapsta.bin"
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#define USB8997_DEFAULT_FW_NAME "mrvl/usbusb8997_combo_v4.bin"
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#define FW_DNLD_TX_BUF_SIZE 620
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#define FW_DNLD_RX_BUF_SIZE 2048
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#define FW_HAS_LAST_BLOCK 0x00000004
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#define FW_CMD_7 0x00000007
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#define FW_DATA_XMIT_SIZE \
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(sizeof(struct fw_header) + dlen + sizeof(u32))
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struct urb_context {
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struct mwifiex_adapter *adapter;
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struct sk_buff *skb;
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struct urb *urb;
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u8 ep;
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};
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#define MWIFIEX_USB_TX_AGGR_TMO_MIN 1
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#define MWIFIEX_USB_TX_AGGR_TMO_MAX 4
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struct tx_aggr_tmr_cnxt {
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struct mwifiex_adapter *adapter;
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struct usb_tx_data_port *port;
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struct timer_list hold_timer;
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bool is_hold_timer_set;
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u32 hold_tmo_msecs;
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};
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struct usb_tx_aggr {
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struct sk_buff_head aggr_list;
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int aggr_len;
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int aggr_num;
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struct tx_aggr_tmr_cnxt timer_cnxt;
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};
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struct usb_tx_data_port {
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u8 tx_data_ep;
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u8 block_status;
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atomic_t tx_data_urb_pending;
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int tx_data_ix;
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struct urb_context tx_data_list[MWIFIEX_TX_DATA_URB];
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/* usb tx aggregation*/
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struct usb_tx_aggr tx_aggr;
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struct sk_buff *skb_aggr[MWIFIEX_TX_DATA_URB];
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/* lock for protect tx aggregation data path*/
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spinlock_t tx_aggr_lock;
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};
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struct usb_card_rec {
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struct mwifiex_adapter *adapter;
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struct usb_device *udev;
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struct usb_interface *intf;
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struct completion fw_done;
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u8 rx_cmd_ep;
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struct urb_context rx_cmd;
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atomic_t rx_cmd_urb_pending;
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struct urb_context rx_data_list[MWIFIEX_RX_DATA_URB];
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u8 usb_boot_state;
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u8 rx_data_ep;
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atomic_t rx_data_urb_pending;
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u8 tx_cmd_ep;
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atomic_t tx_cmd_urb_pending;
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int bulk_out_maxpktsize;
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struct urb_context tx_cmd;
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u8 mc_resync_flag;
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struct usb_tx_data_port port[MWIFIEX_TX_DATA_PORT];
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int rx_cmd_ep_type;
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u8 rx_cmd_interval;
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int tx_cmd_ep_type;
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u8 tx_cmd_interval;
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};
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struct fw_header {
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__le32 dnld_cmd;
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__le32 base_addr;
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__le32 data_len;
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__le32 crc;
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};
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struct fw_sync_header {
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__le32 cmd;
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__le32 seq_num;
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} __packed;
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struct fw_data {
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struct fw_header fw_hdr;
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__le32 seq_num;
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u8 data[1];
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} __packed;
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#endif /*_MWIFIEX_USB_H */
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