linux_dsm_epyc7002/arch/x86/events/intel
Stephane Eranian daa864b8f8 perf/x86/pebs: Fix handling of PEBS buffer overflows
This patch solves a race condition between PEBS and the PMU handler.

In case multiple PEBS events are sampled at the same time,
it is possible to have GLOBAL_STATUS bit 62 set indicating
PEBS buffer overflow and also seeing at most 3 PEBS counters
having their bits set in the status register. This is a sign
that there was at least one PEBS record pending at the time
of the PMU interrupt. PEBS counters must only be processed
via the drain_pebs() calls, and not via the regular sample
processing loop coming after that the function, otherwise
phony regular samples may be generated in the sampling buffer
not marked with the EXACT tag.

Another possibility is to have one PEBS event and at least
one non-PEBS event whic hoverflows while PEBS has armed. In this
case, bit 62 of GLOBAL_STATUS will not be set, yet the overflow
status bit for the PEBS counter will be on Skylake.

To avoid this problem, we systematically ignore the PEBS-enabled
counters from the GLOBAL_STATUS mask and we always process PEBS
events via drain_pebs().

The problem manifested itself by having non-exact samples when
sampling only PEBS events, i.e., the PERF_SAMPLE_RECORD would
not have the EXACT flag set.

Note that this problem is only present on Skylake processor.
This fix is harmless on older processors.

Reported-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1482395366-8992-1-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-12-22 17:45:36 +01:00
..
bts.c perf/x86/intel/bts: Make it an exclusive PMU 2016-09-22 14:56:08 +02:00
core.c perf/x86/pebs: Fix handling of PEBS buffer overflows 2016-12-22 17:45:36 +01:00
cqm.c perf/x86/intel/cqm: Check cqm/mbm enabled state in event init 2016-09-06 10:42:12 +02:00
cstate.c perf/x86/intel: Enable C-state residency events for Knights Mill 2016-12-06 09:44:27 +01:00
ds.c perf/x86/intel: Cure bogus unwind from PEBS entries 2016-11-22 12:36:58 +01:00
knc.c perf/x86/intel: Fix PEBS warning by only restoring active PMU in pmi 2016-03-08 12:18:32 +01:00
lbr.c perf/x86/intel: Remove an inconsistent NULL check 2016-10-16 11:34:14 +02:00
Makefile x86/perf/intel/rapl: Fix module name collision with powercap intel-rapl 2016-07-06 12:51:59 +02:00
p4.c perf/x86/intel/p4: Trival indentation fix, remove space 2016-05-20 09:18:22 +02:00
p6.c perf/x86: Move perf_event.h to its new home 2016-02-17 10:11:36 +01:00
pt.c x86/cpuid: Cleanup cpuid_regs definitions 2016-11-16 11:13:09 +01:00
pt.h perf/x86/intel/pt: Add support for PTWRITE and power event tracing 2016-09-20 01:18:28 +02:00
rapl.c perf/x86/intel/rapl: Add Knights Mill CPUID 2016-10-17 10:45:09 +02:00
uncore_nhmex.c perf/x86/intel/uncore: Clean up hardware on exit 2016-02-29 09:35:15 +01:00
uncore_snb.c perf/x86/uncore: Fix crash by removing bogus event_list[] handling for SNB client uncore IMC 2016-11-16 09:46:35 +01:00
uncore_snbep.c perf/x86/intel/uncore: Add Skylake server uncore support 2016-09-10 11:18:52 +02:00
uncore.c perf/x86/intel/uncore: Allow only a single PMU/box within an events group 2016-11-22 12:36:59 +01:00
uncore.h perf/x86/intel/uncore: Add Skylake server uncore support 2016-09-10 11:18:52 +02:00