mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 06:16:56 +07:00
57471c8d3c
Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
553 lines
12 KiB
Plaintext
553 lines
12 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uarta;
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serial1 = &uartb;
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serial2 = &uartc;
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serial3 = &uartd;
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serial4 = &uarte;
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};
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host1x {
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <0 65 0x04 /* mpcore syncpt */
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0 67 0x04>; /* mpcore general */
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clocks = <&tegra_car 28>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe {
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compatible = "nvidia,tegra20-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <0 68 0x04>;
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clocks = <&tegra_car 60>;
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};
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vi {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car 100>;
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};
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epp {
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <0 70 0x04>;
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clocks = <&tegra_car 19>;
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};
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isp {
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compatible = "nvidia,tegra20-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <0 71 0x04>;
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clocks = <&tegra_car 23>;
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};
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gr2d {
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compatible = "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <0 72 0x04>;
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clocks = <&tegra_car 21>;
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};
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gr3d {
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compatible = "nvidia,tegra20-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car 24>;
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};
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <0 73 0x04>;
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clocks = <&tegra_car 27>, <&tegra_car 121>;
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clock-names = "disp1", "parent";
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <0 74 0x04>;
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clocks = <&tegra_car 26>, <&tegra_car 121>;
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clock-names = "disp2", "parent";
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rgb {
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status = "disabled";
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};
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};
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hdmi {
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <0 75 0x04>;
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clocks = <&tegra_car 51>, <&tegra_car 117>;
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clock-names = "hdmi", "parent";
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status = "disabled";
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};
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tvo {
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <0 76 0x04>;
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clocks = <&tegra_car 102>;
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status = "disabled";
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};
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dsi {
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compatible = "nvidia,tegra20-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car 48>;
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status = "disabled";
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};
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};
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timer@50004600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x50040600 0x20>;
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interrupts = <1 13 0x304>;
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clocks = <&tegra_car 132>;
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};
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intc: interrupt-controller {
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compatible = "arm,cortex-a9-gic";
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reg = <0x50041000 0x1000
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0x50040100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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arm,data-latency = <5 5 2>;
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arm,tag-latency = <4 4 2>;
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cache-unified;
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cache-level = <2>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1200>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04>;
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clocks = <&tegra_car 34>;
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};
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ahb {
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compatible = "nvidia,tegra20-ahb";
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reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
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};
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gpio: gpio {
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compatible = "nvidia,tegra20-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra20-pinmux";
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reg = <0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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0x700000a0 0x14 /* Pull-up/down registers */
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0x70000868 0xa8>; /* Pad control registers */
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};
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das {
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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tegra_ac97: ac97 {
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compatible = "nvidia,tegra20-ac97";
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reg = <0x70002000 0x200>;
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interrupts = <0 81 0x04>;
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nvidia,dma-request-selector = <&apbdma 12>;
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clocks = <&tegra_car 3>;
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status = "disabled";
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};
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tegra_i2s1: i2s@70002800 {
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = <0 13 0x04>;
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nvidia,dma-request-selector = <&apbdma 2>;
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clocks = <&tegra_car 11>;
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status = "disabled";
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};
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tegra_i2s2: i2s@70002a00 {
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = <0 3 0x04>;
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nvidia,dma-request-selector = <&apbdma 1>;
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clocks = <&tegra_car 18>;
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status = "disabled";
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
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* driver, the comptible is "nvidia,tegra20-hsuart".
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*/
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uarta: serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car 6>;
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car 96>;
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car 55>;
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car 65>;
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status = "disabled";
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};
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uarte: serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = <0 91 0x04>;
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nvidia,dma-request-selector = <&apbdma 20>;
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clocks = <&tegra_car 66>;
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status = "disabled";
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};
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pwm: pwm {
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compatible = "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car 17>;
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};
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rtc {
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compatible = "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 12>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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spi@7000c380 {
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compatible = "nvidia,tegra20-sflash";
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reg = <0x7000c380 0x80>;
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interrupts = <0 39 0x04>;
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nvidia,dma-request-selector = <&apbdma 11>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 43>;
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <0 84 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 54>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <0 92 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 67>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra20-i2c-dvc";
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reg = <0x7000d000 0x200>;
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interrupts = <0 53 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 47>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra20-slink";
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reg = <0x7000d400 0x200>;
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interrupts = <0 59 0x04>;
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nvidia,dma-request-selector = <&apbdma 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 41>;
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status = "disabled";
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};
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spi@7000d600 {
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compatible = "nvidia,tegra20-slink";
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reg = <0x7000d600 0x200>;
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interrupts = <0 82 0x04>;
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nvidia,dma-request-selector = <&apbdma 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 44>;
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status = "disabled";
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};
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spi@7000d800 {
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compatible = "nvidia,tegra20-slink";
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reg = <0x7000d800 0x200>;
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interrupts = <0 83 0x04>;
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nvidia,dma-request-selector = <&apbdma 17>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 46>;
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status = "disabled";
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};
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spi@7000da00 {
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compatible = "nvidia,tegra20-slink";
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reg = <0x7000da00 0x200>;
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interrupts = <0 93 0x04>;
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nvidia,dma-request-selector = <&apbdma 18>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 68>;
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status = "disabled";
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};
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kbc {
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compatible = "nvidia,tegra20-kbc";
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reg = <0x7000e200 0x100>;
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interrupts = <0 85 0x04>;
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clocks = <&tegra_car 36>;
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status = "disabled";
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};
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pmc {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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};
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memory-controller@7000f000 {
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compatible = "nvidia,tegra20-mc";
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reg = <0x7000f000 0x024
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0x7000f03c 0x3c4>;
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interrupts = <0 77 0x04>;
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};
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iommu {
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compatible = "nvidia,tegra20-gart";
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reg = <0x7000f024 0x00000018 /* controller registers */
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0x58000000 0x02000000>; /* GART aperture */
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};
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memory-controller@7000f400 {
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f400 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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phy1: usb-phy@c5000400 {
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compatible = "nvidia,tegra20-usb-phy";
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reg = <0xc5000400 0x3c00>;
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phy_type = "utmi";
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nvidia,has-legacy-mode;
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clocks = <&tegra_car 22>, <&tegra_car 127>;
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clock-names = "phy", "pll_u";
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};
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phy2: usb-phy@c5004400 {
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compatible = "nvidia,tegra20-usb-phy";
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reg = <0xc5004400 0x3c00>;
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phy_type = "ulpi";
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clocks = <&tegra_car 94>, <&tegra_car 127>;
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clock-names = "phy", "pll_u";
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};
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phy3: usb-phy@c5008400 {
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compatible = "nvidia,tegra20-usb-phy";
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reg = <0xc5008400 0x3C00>;
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phy_type = "utmi";
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clocks = <&tegra_car 22>, <&tegra_car 127>;
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clock-names = "phy", "pll_u";
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};
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usb@c5000000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5000000 0x4000>;
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interrupts = <0 20 0x04>;
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phy_type = "utmi";
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nvidia,has-legacy-mode;
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clocks = <&tegra_car 22>;
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nvidia,needs-double-reset;
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nvidia,phy = <&phy1>;
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status = "disabled";
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};
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usb@c5004000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5004000 0x4000>;
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interrupts = <0 21 0x04>;
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phy_type = "ulpi";
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clocks = <&tegra_car 58>;
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nvidia,phy = <&phy2>;
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status = "disabled";
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};
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usb@c5008000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5008000 0x4000>;
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interrupts = <0 97 0x04>;
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phy_type = "utmi";
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clocks = <&tegra_car 59>;
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nvidia,phy = <&phy3>;
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status = "disabled";
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = <0 14 0x04>;
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clocks = <&tegra_car 14>;
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status = "disabled";
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = <0 15 0x04>;
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clocks = <&tegra_car 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000400 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000400 0x200>;
|
|
interrupts = <0 19 0x04>;
|
|
clocks = <&tegra_car 69>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&tegra_car 15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 56 0x04
|
|
0 57 0x04>;
|
|
};
|
|
};
|