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Buffer manager (BM) is a dedicated hardware unit that can be used by all
ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
path by sparing DRAM access on refilling buffer pool, hardware-based
filling of descriptor ring data and better memory utilization due to HW
arbitration for using 'short' pools for small packets.
Tests performed with A388 SoC working as a network bridge between two
packet generators showed increase of maximum processed 64B packets by
~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
when pushing 1500B-packets with a line rate achieved, CPU load decreased
from around 25% without BM to 20% with BM.
BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
are called external BP pools - BPPE. Allocating and releasing buffer
pointers (BP) to/from BPPE is performed indirectly by write/read access
to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
BM hardware controls status of BPPE automatically, as well as assigning
proper buffers to RX descriptors. For more details please refer to
Functional Specification of Armada XP or 38x SoC.
In order to enable support for a separate hardware block, common for all
ports, a new driver has to be implemented ('mvneta_bm'). It provides
initialization sequence of address space, clocks, registers, SRAM,
empty pools' structures and also obtaining optional configuration
from DT (please refer to device tree binding documentation). mvneta_bm
exposes also a necessary API to mvneta driver, as well as a dedicated
structure with BM information (bm_priv), whose presence is used as a
flag notifying of BM usage by port. It has to be ensured that mvneta_bm
probe is executed prior to the ones in ports' driver. In case BM is not
used or its probe fails, mvneta falls back to use software buffer
management.
A sequence executed in mvneta_probe function is modified in order to have
an access to needed resources before possible port's BM initialization is
done. According to port-pools mapping provided by DT appropriate registers
are configured and the buffer pools are filled. RX path is modified
accordingly. Becaues the hardware allows a wide variety of configuration
options, following assumptions are made:
* using BM mechanisms can be selectively disabled/enabled basing
on DT configuration among the ports
* 'long' pool's single buffer size is tied to port's MTU
* using 'long' pool by port is obligatory and it cannot be shared
* using 'short' pool for smaller packets is optional
* one 'short' pool can be shared among all ports
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clement@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
48 lines
1.7 KiB
Plaintext
48 lines
1.7 KiB
Plaintext
* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
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Required properties:
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- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
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- reg: address and length of the register set for the device.
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- interrupts: interrupt for the device
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- phy: See ethernet.txt file in the same directory.
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- phy-mode: See ethernet.txt file in the same directory
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- clocks: List of clocks for this device. At least one clock is
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mandatory for the core clock. If several clocks are given, then the
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clock-names property must be used to identify them.
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Optional properties:
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- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
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Value is presented in bytes. If not used, by default 1600B is set for
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"marvell,armada-370-neta" and 9800B for others.
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- clock-names: List of names corresponding to clocks property; shall be
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"core" for core clock and "bus" for the optional bus clock.
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Optional properties (valid only for Armada XP/38x):
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- buffer-manager: a phandle to a buffer manager node. Please refer to
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Documentation/devicetree/bindings/net/marvell-neta-bm.txt
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- bm,pool-long: ID of a pool, that will accept all packets of a size
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higher than 'short' pool's threshold (if set) and up to MTU value.
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Obligatory, when the port is supposed to use hardware
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buffer management.
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- bm,pool-short: ID of a pool, that will be used for accepting
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packets of a size lower than given threshold. If not set, the port
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will use a single 'long' pool for all packets, as defined above.
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Example:
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ethernet@70000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x70000 0x2500>;
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interrupts = <8>;
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clocks = <&gate_clk 4>;
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tx-csum-limit = <9800>
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <1>;
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};
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