mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 06:21:34 +07:00
383 lines
14 KiB
C
383 lines
14 KiB
C
#ifndef A6XX_GMU_XML
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#define A6XX_GMU_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
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#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
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#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
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#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
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#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
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#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
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#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
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#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
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#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
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#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
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#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
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#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
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#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
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#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
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#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
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#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
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#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
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#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
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#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
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#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
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static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
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{
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return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK;
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}
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#define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000
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#define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24
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static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
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{
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return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
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}
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#define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
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#define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
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#define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
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#define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00
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#define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00
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#define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0
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#define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8
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#define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9
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#define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa
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#define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc
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#define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd
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#define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe
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#define REG_A6XX_GMU_DCVS_RETURN 0x000023ff
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#define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f
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#define REG_A6XX_GMU_CM3_SYSRESET 0x00005000
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#define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001
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#define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a
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#define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c
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#define REG_A6XX_GMU_CM3_CFG 0x0000502d
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e
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#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f
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#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10
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static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
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{
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return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK;
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}
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000
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#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14
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static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
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{
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return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK;
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}
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#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1
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#define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2
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#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
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#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080
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#define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4
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#define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001
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#define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0
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#define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4
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static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
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{
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return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK;
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}
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#define REG_A6XX_GMU_RPMH_CTRL 0x000050e8
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#define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001
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#define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010
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#define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100
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#define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200
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#define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400
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#define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800
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#define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000
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#define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000
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#define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000
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#define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000
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#define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9
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#define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec
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#define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0
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#define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157
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#define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158
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#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088
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#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089
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#define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3
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#define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180
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#define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181
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#define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182
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#define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183
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#define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184
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#define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185
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#define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186
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#define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190
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#define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191
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#define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192
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#define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001
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#define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000
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#define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193
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#define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194
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#define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195
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#define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196
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#define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197
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#define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198
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#define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199
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#define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a
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#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b
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#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c
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#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d
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#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
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#define REG_A6XX_GMU_GENERAL_1 0x000051c6
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#define REG_A6XX_GMU_GENERAL_7 0x000051cc
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#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
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#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
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#define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558
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#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580
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#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada
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#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957
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#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
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#define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d
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#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
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#define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d
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#define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303
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#define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304
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#define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010
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#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020
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#define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306
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#define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309
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#define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a
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#define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b
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#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c
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#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000
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#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d
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#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e
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#define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310
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#define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
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#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
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#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
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#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04
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#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
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#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
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#define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311
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#define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312
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#define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
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#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
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#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09
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#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a
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#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d
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#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89
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#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c
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#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00
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#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01
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#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80
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#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46
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#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae
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#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216
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#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e
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#endif /* A6XX_GMU_XML */
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