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d9ff80f83e
During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed. Instruction fetches are not subject to the conditions of this erratum. If the original code sequence includes multiple TLB invalidate instructions followed by a single DSB, onle one of the TLB instructions needs to be repeated to work around this erratum. While the erratum only applies to cases in which the TLBI specifies the inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or stronger (OSH, SYS), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Christopher Covington <cov@codeaurora.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
178 lines
4.8 KiB
C
178 lines
4.8 KiB
C
/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
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entry->midr_range_min,
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entry->midr_range_max);
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}
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static bool
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has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
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}
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static int cpu_enable_trap_ctr_access(void *__unused)
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{
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/* Clear SCTLR_EL1.UCT */
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config_sctlr_el1(SCTLR_EL1_UCT, 0);
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return 0;
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}
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#define MIDR_RANGE(model, min, max) \
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.def_scope = SCOPE_LOCAL_CPU, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = min, \
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.midr_range_max = max
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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defined(CONFIG_ARM64_ERRATUM_824069)
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{
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/* Cortex-A53 r0p[012] */
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.desc = "ARM errata 826319, 827319, 824069",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
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.enable = cpu_enable_cache_maint_trap,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_819472
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{
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/* Cortex-A53 r0p[01] */
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.desc = "ARM errata 819472",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
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.enable = cpu_enable_cache_maint_trap,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_832075
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 832075",
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.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_834220
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 834220",
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.capability = ARM64_WORKAROUND_834220,
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MIDR_RANGE(MIDR_CORTEX_A57,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 2)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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{
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 845719",
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_23154
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{
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/* Cavium ThunderX, pass 1.x */
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.desc = "Cavium erratum 23154",
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.capability = ARM64_WORKAROUND_CAVIUM_23154,
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MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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{
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/* Cavium ThunderX, T88 pass 1.x - 2.1 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, 1)),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
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},
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#endif
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{
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.desc = "Mismatched cache line size",
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.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
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.matches = has_mismatched_cache_line_size,
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.def_scope = SCOPE_LOCAL_CPU,
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.enable = cpu_enable_trap_ctr_access,
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},
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
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{
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.desc = "Qualcomm Technologies Falkor erratum 1009",
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.capability = ARM64_WORKAROUND_REPEAT_TLBI,
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MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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},
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#endif
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{
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}
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};
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/*
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* The CPU Errata work arounds are detected and applied at boot time
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* and the related information is freed soon after. If the new CPU requires
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* an errata not detected at boot, fail this CPU.
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*/
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void verify_local_cpu_errata_workarounds(void)
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{
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const struct arm64_cpu_capabilities *caps = arm64_errata;
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for (; caps->matches; caps++)
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if (!cpus_have_cap(caps->capability) &&
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caps->matches(caps, SCOPE_LOCAL_CPU)) {
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pr_crit("CPU%d: Requires work around for %s, not detected"
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" at boot time\n",
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smp_processor_id(),
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caps->desc ? : "an erratum");
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cpu_die_early();
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}
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}
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void update_cpu_errata_workarounds(void)
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{
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update_cpu_capabilities(arm64_errata, "enabling workaround for");
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}
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void __init enable_errata_workarounds(void)
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{
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enable_cpu_capabilities(arm64_errata);
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}
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