mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 14:05:46 +07:00
cd6a851385
Avoid going to the base i915 device when we already have a path from gt to the runtime powermanagement interface. The benefit is that it looks a bit more self-consistent to always be acquiring the gt->uncore->rpm for use with the gt->uncore. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191007154531.1750-1-chris@chris-wilson.co.uk
405 lines
9.8 KiB
C
405 lines
9.8 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_pm.h"
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#include "intel_gt_requests.h"
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#include "intel_mocs.h"
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#include "intel_rc6.h"
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#include "intel_uncore.h"
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#include "intel_pm.h"
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void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
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{
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gt->i915 = i915;
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gt->uncore = &i915->uncore;
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spin_lock_init(>->irq_lock);
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INIT_LIST_HEAD(>->closed_vma);
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spin_lock_init(>->closed_lock);
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intel_gt_init_hangcheck(gt);
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intel_gt_init_reset(gt);
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intel_gt_init_requests(gt);
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intel_gt_pm_init_early(gt);
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intel_uc_init_early(>->uc);
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}
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void intel_gt_init_hw_early(struct drm_i915_private *i915)
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{
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i915->gt.ggtt = &i915->ggtt;
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/* BIOS often leaves RC6 enabled, but disable it for hw init */
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intel_gt_pm_disable(&i915->gt);
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}
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static void init_unused_ring(struct intel_gt *gt, u32 base)
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{
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struct intel_uncore *uncore = gt->uncore;
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intel_uncore_write(uncore, RING_CTL(base), 0);
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intel_uncore_write(uncore, RING_HEAD(base), 0);
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intel_uncore_write(uncore, RING_TAIL(base), 0);
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intel_uncore_write(uncore, RING_START(base), 0);
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}
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static void init_unused_rings(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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if (IS_I830(i915)) {
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init_unused_ring(gt, PRB1_BASE);
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init_unused_ring(gt, SRB0_BASE);
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init_unused_ring(gt, SRB1_BASE);
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init_unused_ring(gt, SRB2_BASE);
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init_unused_ring(gt, SRB3_BASE);
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} else if (IS_GEN(i915, 2)) {
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init_unused_ring(gt, SRB0_BASE);
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init_unused_ring(gt, SRB1_BASE);
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} else if (IS_GEN(i915, 3)) {
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init_unused_ring(gt, PRB1_BASE);
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init_unused_ring(gt, PRB2_BASE);
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}
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}
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int intel_gt_init_hw(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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int ret;
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BUG_ON(!i915->kernel_context);
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ret = intel_gt_terminally_wedged(gt);
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if (ret)
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return ret;
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gt->last_init_time = ktime_get();
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/* Double layer security blanket, see i915_gem_init() */
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
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intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
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if (IS_HASWELL(i915))
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intel_uncore_write(uncore,
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MI_PREDICATE_RESULT_2,
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IS_HSW_GT3(i915) ?
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LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
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/* Apply the GT workarounds... */
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intel_gt_apply_workarounds(gt);
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/* ...and determine whether they are sticking. */
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intel_gt_verify_workarounds(gt, "init");
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intel_gt_init_swizzling(gt);
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/*
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* At least 830 can leave some of the unused rings
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* "active" (ie. head != tail) after resume which
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* will prevent c3 entry. Makes sure all unused rings
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* are totally idle.
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*/
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init_unused_rings(gt);
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ret = i915_ppgtt_init_hw(gt);
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if (ret) {
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DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
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goto out;
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}
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/* We can't enable contexts until all firmware is loaded */
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ret = intel_uc_init_hw(>->uc);
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if (ret) {
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i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
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goto out;
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}
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intel_mocs_init(gt);
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out:
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intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
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return ret;
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}
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static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
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{
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intel_uncore_rmw(uncore, reg, 0, set);
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}
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static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
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{
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intel_uncore_rmw(uncore, reg, clr, 0);
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}
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static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
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{
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intel_uncore_rmw(uncore, reg, 0, 0);
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}
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static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
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{
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GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
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GEN6_RING_FAULT_REG_POSTING_READ(engine);
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}
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void
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intel_gt_clear_error_registers(struct intel_gt *gt,
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intel_engine_mask_t engine_mask)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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u32 eir;
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if (!IS_GEN(i915, 2))
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clear_register(uncore, PGTBL_ER);
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if (INTEL_GEN(i915) < 4)
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clear_register(uncore, IPEIR(RENDER_RING_BASE));
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else
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clear_register(uncore, IPEIR_I965);
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clear_register(uncore, EIR);
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eir = intel_uncore_read(uncore, EIR);
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if (eir) {
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/*
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* some errors might have become stuck,
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* mask them.
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*/
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DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
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rmw_set(uncore, EMR, eir);
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intel_uncore_write(uncore, GEN2_IIR,
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I915_MASTER_ERROR_INTERRUPT);
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}
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if (INTEL_GEN(i915) >= 12) {
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rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
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intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
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} else if (INTEL_GEN(i915) >= 8) {
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rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
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intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
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} else if (INTEL_GEN(i915) >= 6) {
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine_masked(engine, i915, engine_mask, id)
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gen8_clear_engine_error_register(engine);
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}
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}
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static void gen6_check_faults(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 fault;
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for_each_engine(engine, gt->i915, id) {
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fault = GEN6_RING_FAULT_REG_READ(engine);
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if (fault & RING_FAULT_VALID) {
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08lx\n"
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"\tAddress space: %s\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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fault & PAGE_MASK,
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fault & RING_FAULT_GTTSEL_MASK ?
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"GGTT" : "PPGTT",
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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}
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static void gen8_check_faults(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
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u32 fault;
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if (INTEL_GEN(gt->i915) >= 12) {
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fault_reg = GEN12_RING_FAULT_REG;
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fault_data0_reg = GEN12_FAULT_TLB_DATA0;
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fault_data1_reg = GEN12_FAULT_TLB_DATA1;
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} else {
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fault_reg = GEN8_RING_FAULT_REG;
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fault_data0_reg = GEN8_FAULT_TLB_DATA0;
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fault_data1_reg = GEN8_FAULT_TLB_DATA1;
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}
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fault = intel_uncore_read(uncore, fault_reg);
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if (fault & RING_FAULT_VALID) {
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u32 fault_data0, fault_data1;
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u64 fault_addr;
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fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
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fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
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fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
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((u64)fault_data0 << 12);
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08x_%08x\n"
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"\tAddress space: %s\n"
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"\tEngine ID: %d\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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upper_32_bits(fault_addr),
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lower_32_bits(fault_addr),
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fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
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GEN8_RING_FAULT_ENGINE_ID(fault),
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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void intel_gt_check_and_clear_faults(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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/* From GEN8 onwards we only have one 'All Engine Fault Register' */
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if (INTEL_GEN(i915) >= 8)
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gen8_check_faults(gt);
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else if (INTEL_GEN(i915) >= 6)
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gen6_check_faults(gt);
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else
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return;
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intel_gt_clear_error_registers(gt, ALL_ENGINES);
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}
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void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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intel_wakeref_t wakeref;
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/*
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* No actual flushing is required for the GTT write domain for reads
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* from the GTT domain. Writes to it "immediately" go to main memory
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* as far as we know, so there's no chipset flush. It also doesn't
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* land in the GPU render cache.
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*
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* However, we do have to enforce the order so that all writes through
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* the GTT land before any writes to the device, such as updates to
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* the GATT itself.
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*
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* We also have to wait a bit for the writes to land from the GTT.
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* An uncached read (i.e. mmio) seems to be ideal for the round-trip
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* timing. This issue has only been observed when switching quickly
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* between GTT writes and CPU reads from inside the kernel on recent hw,
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* and it appears to only affect discrete GTT blocks (i.e. on LLC
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* system agents we cannot reproduce this behaviour, until Cannonlake
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* that was!).
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*/
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wmb();
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if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
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return;
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intel_gt_chipset_flush(gt);
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with_intel_runtime_pm(uncore->rpm, wakeref) {
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unsigned long flags;
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spin_lock_irqsave(&uncore->lock, flags);
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intel_uncore_posting_read_fw(uncore,
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RING_HEAD(RENDER_RING_BASE));
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spin_unlock_irqrestore(&uncore->lock, flags);
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}
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}
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void intel_gt_chipset_flush(struct intel_gt *gt)
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{
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wmb();
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if (INTEL_GEN(gt->i915) < 6)
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intel_gtt_chipset_flush();
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}
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void intel_gt_driver_register(struct intel_gt *gt)
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{
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if (IS_GEN(gt->i915, 5))
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intel_gpu_ips_init(gt->i915);
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}
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static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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obj = i915_gem_object_create_stolen(i915, size);
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if (IS_ERR(obj))
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obj = i915_gem_object_create_internal(i915, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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return PTR_ERR(obj);
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}
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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gt->scratch = i915_vma_make_unshrinkable(vma);
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return 0;
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err_unref:
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i915_gem_object_put(obj);
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return ret;
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}
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static void intel_gt_fini_scratch(struct intel_gt *gt)
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{
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i915_vma_unpin_and_release(>->scratch, 0);
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}
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int intel_gt_init(struct intel_gt *gt)
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{
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int err;
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err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
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if (err)
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return err;
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intel_gt_pm_init(gt);
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return 0;
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}
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void intel_gt_driver_remove(struct intel_gt *gt)
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{
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GEM_BUG_ON(gt->awake);
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intel_gt_pm_disable(gt);
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}
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void intel_gt_driver_unregister(struct intel_gt *gt)
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{
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intel_gpu_ips_teardown();
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}
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void intel_gt_driver_release(struct intel_gt *gt)
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{
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/* Paranoia: make sure we have disabled everything before we exit. */
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intel_gt_pm_disable(gt);
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intel_gt_pm_fini(gt);
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intel_gt_fini_scratch(gt);
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}
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void intel_gt_driver_late_release(struct intel_gt *gt)
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{
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intel_uc_driver_late_release(>->uc);
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intel_gt_fini_reset(gt);
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}
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