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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 22:06:49 +07:00
9cf7172893
The endianness of memory accesses at EL2 and EL1 are configured by
SCTLR_EL2.EE and SCTLR_EL1.EE respectively. When the kernel is booted,
the state of SCTLR_EL{2,1}.EE is unknown, and thus the kernel must
ensure that they are set before performing any memory accesses.
This patch ensures that SCTLR_EL{2,1} are configured appropriately at
boot for kernels of either endianness.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[catalin.marinas@arm.com: fix SCTLR_EL1.E0E bit setting in head.S]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
171 lines
4.1 KiB
ArmAsm
171 lines
4.1 KiB
ArmAsm
/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#ifndef CONFIG_SMP
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/* PTWs cacheable, inner/outer WBWA not shareable */
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#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#else
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/* PTWs cacheable, inner/outer WBWA shareable */
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#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
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#endif
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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/*
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* cpu_cache_off()
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*
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* Turn the CPU D-cache off.
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*/
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ENTRY(cpu_cache_off)
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 2 // clear SCTLR.C
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msr sctlr_el1, x0
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isb
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ret
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ENDPROC(cpu_cache_off)
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/*
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* cpu_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the same state
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* as it would be if it had been reset, and branch to what would be the
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* reset vector. It must be executed with the flat identity mapping.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_reset)
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mrs x1, sctlr_el1
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bic x1, x1, #1
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msr sctlr_el1, x1 // disable the MMU
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isb
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ret x0
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ENDPROC(cpu_reset)
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*/
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ENTRY(cpu_do_idle)
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dsb sy // WFI may enter a low-power mode
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wfi
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ret
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ENDPROC(cpu_do_idle)
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/*
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* cpu_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys.
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*
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* - pgd_phys - physical address of new TTB
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*/
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ENTRY(cpu_do_switch_mm)
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mmid w1, x1 // get mm->context.id
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bfi x0, x1, #48, #16 // set the ASID
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msr ttbr0_el1, x0 // set TTBR0
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isb
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ret
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ENDPROC(cpu_do_switch_mm)
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.section ".text.init", #alloc, #execinstr
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/*
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* __cpu_setup
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*
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* Initialise the processor for turning the MMU on. Return in x0 the
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* value of the SCTLR_EL1 register.
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*/
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ENTRY(__cpu_setup)
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/*
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* Preserve the link register across the function call.
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*/
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mov x28, lr
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bl __flush_dcache_all
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mov lr, x28
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ic iallu // I+BTB cache invalidate
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dsb sy
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mov x0, #3 << 20
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msr cpacr_el1, x0 // Enable FP/ASIMD
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msr mdscr_el1, xzr // Reset mdscr_el1
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tlbi vmalle1is // invalidate I + D TLBs
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/*
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* Memory region attributes for LPAE:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* DEVICE_nGnRE 001 00000100
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* DEVICE_GRE 010 00001100
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* NORMAL_NC 011 01000100
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* NORMAL 100 11111111
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*/
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ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
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MAIR(0x04, MT_DEVICE_nGnRE) | \
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MAIR(0x0c, MT_DEVICE_GRE) | \
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MAIR(0x44, MT_NORMAL_NC) | \
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MAIR(0xff, MT_NORMAL)
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msr mair_el1, x5
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/*
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* Prepare SCTLR
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*/
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adr x5, crval
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ldp w5, w6, [x5]
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mrs x0, sctlr_el1
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bic x0, x0, x5 // clear bits
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orr x0, x0, x6 // set bits
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/*
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* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
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* both user and kernel.
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*/
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
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TCR_ASID16 | TCR_TBI0 | (1 << 31)
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#ifdef CONFIG_ARM64_64K_PAGES
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orr x10, x10, TCR_TG0_64K
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orr x10, x10, TCR_TG1_64K
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#endif
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msr tcr_el1, x10
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ret // return to head.S
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ENDPROC(__cpu_setup)
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/*
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* n n T
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* U E WT T UD US IHBS
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* CE0 XWHW CZ ME TEEA S
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* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
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* 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
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* .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings
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*/
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.type crval, #object
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crval:
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.word 0x000802e2 // clear
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.word 0x0405d11d // set
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