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274c27b1f1
device tree bindings for LPDDR2 SDRAM memories compliant to JESD209-2 standard. The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings' for specifying the AC timing parameters of the memory device at different speed-bins. Reviewed-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> [santosh.shilimkar@ti.com: Rebased against 3.6-rc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
103 lines
2.5 KiB
Plaintext
103 lines
2.5 KiB
Plaintext
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
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Required properties:
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- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
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"jedec,lpddr2-s4"
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"ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
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"ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
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"ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
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- density : <u32> representing density in Mb (Mega bits)
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- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
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Optional properties:
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The following optional properties represent the minimum value of some AC
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timing parameters of the DDR device in terms of number of clock cycles.
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These values shall be obtained from the device data-sheet.
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- tRRD-min-tck
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- tWTR-min-tck
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- tXP-min-tck
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- tRTP-min-tck
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- tCKE-min-tck
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- tRPab-min-tck
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- tRCD-min-tck
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- tWR-min-tck
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- tRASmin-min-tck
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- tCKESR-min-tck
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- tFAW-min-tck
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Child nodes:
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- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
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"lpddr2-timings" provides AC timing parameters of the device for
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a given speed-bin. The user may provide the timings for as many
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speed-bins as is required. Please see Documentation/devicetree/
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bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
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Example:
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elpida_ECB240ABACN : lpddr2 {
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compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
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density = <2048>;
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io-width = <32>;
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tRPab-min-tck = <3>;
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tRCD-min-tck = <3>;
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tWR-min-tck = <3>;
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tRASmin-min-tck = <3>;
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tRRD-min-tck = <2>;
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tWTR-min-tck = <2>;
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tXP-min-tck = <2>;
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tRTP-min-tck = <2>;
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tCKE-min-tck = <3>;
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tCKESR-min-tck = <3>;
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tFAW-min-tck = <8>;
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timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
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compatible = "jedec,lpddr2-timings";
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min-freq = <10000000>;
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max-freq = <400000000>;
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tRPab = <21000>;
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tRCD = <18000>;
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tWR = <15000>;
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tRAS-min = <42000>;
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tRRD = <10000>;
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tWTR = <7500>;
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tXP = <7500>;
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tRTP = <7500>;
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tCKESR = <15000>;
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tDQSCK-max = <5500>;
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tFAW = <50000>;
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tZQCS = <90000>;
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tZQCL = <360000>;
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tZQinit = <1000000>;
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tRAS-max-ns = <70000>;
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};
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timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
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compatible = "jedec,lpddr2-timings";
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min-freq = <10000000>;
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max-freq = <200000000>;
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tRPab = <21000>;
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tRCD = <18000>;
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tWR = <15000>;
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tRAS-min = <42000>;
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tRRD = <10000>;
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tWTR = <10000>;
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tXP = <7500>;
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tRTP = <7500>;
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tCKESR = <15000>;
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tDQSCK-max = <5500>;
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tFAW = <50000>;
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tZQCS = <90000>;
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tZQCL = <360000>;
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tZQinit = <1000000>;
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tRAS-max-ns = <70000>;
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};
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}
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