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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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319b15df66
If the R-Car system controller is described in DT, the rcar-sysc driver
configures SYSCIER and SYSCIMR based on the SoC-specific power area
definitions in r8a779*-sysc. The platform code still passed this
information to the rcar-sysc driver, for compatibility with old R-Car H2
and M2-W DTBs predating commit 8574de8619 ("ARM: dts: r8a7791: Add
SYSC PM Domains") in v4.7. The time has come to drop backwards
compatibility, and delegate everything to the DT enabled rcar-sysc
driver.
After the removal of the legacy SMP fallbacks, which powered up the SCUs
explicitly, there is no longer a need to force an early initialization
of the rcar-sysc driver. It will be initialized in time for secondary
CPU bringup by its early_initcall().
Hence all explicit SYSC configuration and initialization can be removed
from the R-Car Gen2 platform code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/*
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* R-Car Generation 2 Power management support
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*
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* Copyright (C) 2013 - 2015 Renesas Electronics Corporation
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/io.h>
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#include <asm/cputype.h>
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#include "common.h"
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#include "rcar-gen2.h"
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/* RST */
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#define RST 0xe6160000
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#define CA15BAR 0x0020 /* CA15 Boot Address Register */
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#define CA7BAR 0x0030 /* CA7 Boot Address Register */
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#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
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#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
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/* SYS Boot Address Register */
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#define SBAR_BAREN BIT(4) /* SBAR is valid */
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/* Reset Control Registers */
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#define CA15RESCNT_CODE 0xa5a50000
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#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
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#define CA7RESCNT_CODE 0x5a5a0000
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#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
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/* On-chip RAM */
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#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
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static inline u32 phys_to_sbar(phys_addr_t addr)
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{
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return (addr >> 8) & 0xfffffc00;
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}
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void __init rcar_gen2_pm_init(void)
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{
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void __iomem *p;
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u32 bar;
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static int once;
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struct device_node *np, *cpus;
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bool has_a7 = false;
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bool has_a15 = false;
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struct resource res;
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int error;
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if (once++)
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return;
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cpus = of_find_node_by_path("/cpus");
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if (!cpus)
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return;
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for_each_child_of_node(cpus, np) {
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if (of_device_is_compatible(np, "arm,cortex-a15"))
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has_a15 = true;
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else if (of_device_is_compatible(np, "arm,cortex-a7"))
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has_a7 = true;
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}
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np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
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if (!np) {
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/* No smp-sram in DT, fall back to hardcoded address */
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res = (struct resource)DEFINE_RES_MEM(ICRAM1,
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shmobile_boot_size);
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goto map;
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}
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error = of_address_to_resource(np, 0, &res);
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if (error) {
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pr_err("Failed to get smp-sram address: %d\n", error);
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return;
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}
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map:
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/* RAM for jump stub, because BAR requires 256KB aligned address */
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if (res.start & (256 * 1024 - 1) ||
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resource_size(&res) < shmobile_boot_size) {
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pr_err("Invalid smp-sram region\n");
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return;
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}
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p = ioremap(res.start, resource_size(&res));
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if (!p)
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return;
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/*
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* install the reset vector, use the largest version if we have enough
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* memory available
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*/
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if (resource_size(&res) >= shmobile_boot_size_gen2) {
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shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
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memcpy_toio(p, shmobile_boot_vector_gen2,
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shmobile_boot_size_gen2);
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} else {
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memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
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}
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iounmap(p);
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/* setup reset vectors */
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p = ioremap_nocache(RST, 0x63);
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bar = phys_to_sbar(res.start);
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if (has_a15) {
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writel_relaxed(bar, p + CA15BAR);
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writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
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/* de-assert reset for CA15 CPUs */
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writel_relaxed((readl_relaxed(p + CA15RESCNT) &
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~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
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p + CA15RESCNT);
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}
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if (has_a7) {
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writel_relaxed(bar, p + CA7BAR);
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writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
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/* de-assert reset for CA7 CPUs */
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writel_relaxed((readl_relaxed(p + CA7RESCNT) &
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~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
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p + CA7RESCNT);
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}
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iounmap(p);
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shmobile_smp_apmu_suspend_init();
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}
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