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d91cab7813
There are two concepts that have some confusing naming: 1. Extended State Component numbers (currently called XFEATURE_BIT_*) 2. Extended State Component masks (currently called XSTATE_*) The numbers are (currently) from 0-9. State component 3 is the bounds registers for MPX, for instance. But when we want to enable "state component 3", we go set a bit in XCR0. The bit we set is 1<<3. We can check to see if a state component feature is enabled by looking at its bit. The current 'xfeature_bit's are at best xfeature bit _numbers_. Calling them bits is at best inconsistent with ending the enum list with 'XFEATURES_NR_MAX'. This patch renames the enum to be 'xfeature'. These also happen to be what the Intel documentation calls a "state component". We also want to differentiate these from the "XSTATE_*" macros. The "XSTATE_*" macros are a mask, and we rename them to match. These macros are reasonably widely used so this patch is a wee bit big, but this really is just a rename. The only non-mechanical part of this is the s/XSTATE_EXTEND_MASK/XFEATURE_MASK_EXTEND/ We need a better name for it, but that's another patch. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tim Chen <tim.c.chen@linux.intel.com> Cc: dave@sr71.net Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/20150902233126.38653250@viggo.jf.intel.com [ Ported to v4.3-rc1. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
192 lines
5.2 KiB
C
192 lines
5.2 KiB
C
/*
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* Cryptographic API.
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*
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* Glue code for the SHA256 Secure Hash Algorithm assembler
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* implementation using supplemental SSE3 / AVX / AVX2 instructions.
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*
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* This file is based on sha256_generic.c
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*
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* Copyright (C) 2013 Intel Corporation.
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*
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* Author:
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* Tim Chen <tim.c.chen@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/cryptohash.h>
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#include <linux/types.h>
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#include <crypto/sha.h>
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#include <crypto/sha256_base.h>
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#include <asm/fpu/api.h>
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#include <linux/string.h>
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asmlinkage void sha256_transform_ssse3(u32 *digest, const char *data,
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u64 rounds);
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#ifdef CONFIG_AS_AVX
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asmlinkage void sha256_transform_avx(u32 *digest, const char *data,
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u64 rounds);
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#endif
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#ifdef CONFIG_AS_AVX2
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asmlinkage void sha256_transform_rorx(u32 *digest, const char *data,
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u64 rounds);
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#endif
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static void (*sha256_transform_asm)(u32 *, const char *, u64);
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static int sha256_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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if (!irq_fpu_usable() ||
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(sctx->count % SHA256_BLOCK_SIZE) + len < SHA256_BLOCK_SIZE)
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return crypto_sha256_update(desc, data, len);
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/* make sure casting to sha256_block_fn() is safe */
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BUILD_BUG_ON(offsetof(struct sha256_state, state) != 0);
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kernel_fpu_begin();
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sha256_base_do_update(desc, data, len,
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(sha256_block_fn *)sha256_transform_asm);
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kernel_fpu_end();
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return 0;
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}
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static int sha256_ssse3_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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if (!irq_fpu_usable())
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return crypto_sha256_finup(desc, data, len, out);
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kernel_fpu_begin();
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if (len)
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sha256_base_do_update(desc, data, len,
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(sha256_block_fn *)sha256_transform_asm);
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sha256_base_do_finalize(desc, (sha256_block_fn *)sha256_transform_asm);
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kernel_fpu_end();
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return sha256_base_finish(desc, out);
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}
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/* Add padding and return the message digest. */
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static int sha256_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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return sha256_ssse3_finup(desc, NULL, 0, out);
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}
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static struct shash_alg algs[] = { {
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.digestsize = SHA256_DIGEST_SIZE,
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.init = sha256_base_init,
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.update = sha256_ssse3_update,
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.final = sha256_ssse3_final,
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.finup = sha256_ssse3_finup,
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.descsize = sizeof(struct sha256_state),
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.base = {
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.cra_name = "sha256",
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.cra_driver_name = "sha256-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA256_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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}, {
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.digestsize = SHA224_DIGEST_SIZE,
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.init = sha224_base_init,
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.update = sha256_ssse3_update,
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.final = sha256_ssse3_final,
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.finup = sha256_ssse3_finup,
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.descsize = sizeof(struct sha256_state),
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.base = {
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.cra_name = "sha224",
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.cra_driver_name = "sha224-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA224_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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} };
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#ifdef CONFIG_AS_AVX
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static bool __init avx_usable(void)
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{
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if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL)) {
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if (cpu_has_avx)
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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#endif
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static int __init sha256_ssse3_mod_init(void)
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{
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/* test for SSSE3 first */
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if (cpu_has_ssse3)
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sha256_transform_asm = sha256_transform_ssse3;
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#ifdef CONFIG_AS_AVX
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/* allow AVX to override SSSE3, it's a little faster */
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if (avx_usable()) {
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#ifdef CONFIG_AS_AVX2
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if (boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_BMI2))
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sha256_transform_asm = sha256_transform_rorx;
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else
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#endif
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sha256_transform_asm = sha256_transform_avx;
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}
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#endif
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if (sha256_transform_asm) {
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#ifdef CONFIG_AS_AVX
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if (sha256_transform_asm == sha256_transform_avx)
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pr_info("Using AVX optimized SHA-256 implementation\n");
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#ifdef CONFIG_AS_AVX2
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else if (sha256_transform_asm == sha256_transform_rorx)
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pr_info("Using AVX2 optimized SHA-256 implementation\n");
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#endif
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else
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#endif
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pr_info("Using SSSE3 optimized SHA-256 implementation\n");
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return crypto_register_shashes(algs, ARRAY_SIZE(algs));
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}
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pr_info("Neither AVX nor SSSE3 is available/usable.\n");
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return -ENODEV;
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}
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static void __exit sha256_ssse3_mod_fini(void)
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{
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crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
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}
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module_init(sha256_ssse3_mod_init);
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module_exit(sha256_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS_CRYPTO("sha256");
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MODULE_ALIAS_CRYPTO("sha224");
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