mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 08:25:20 +07:00
fb7d38a70e
On Meson8b the only valid input clock is MPLL2. The bootloader
configures that to run at 500002394Hz which cannot be divided evenly
down to 125MHz using the m250_div clock. Currently the common clock
framework chooses a m250_div of 2 - with the internal fixed
"divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz
above the requested 125MHz).
Letting the common clock framework propagate the rate changes up to the
parent of m250_mux allows us to get the best possible clock rate. With
this patch the common clock framework calculates a rate of
very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock
(which is the mux input). Dividing that by 2 (which is an internal,
fixed divider for the RGMII TX clock) gives us an RGMII TX clock of
124999850Hz (which is only 150Hz off the requested 125MHz, compared to
1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel
sources).
SoCs from the Meson GX series are not affected by this change because
the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine
since it's running at 1GHz, so it's already a multiple of 250MHz and
125MHz).
Fixes: 566e825162
("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC")
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
364 lines
10 KiB
C
364 lines
10 KiB
C
/*
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* Amlogic Meson8b and GXBB DWMAC glue layer
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*
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define PRG_ETH0 0x0
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#define PRG_ETH0_RGMII_MODE BIT(0)
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/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
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#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
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#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
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#define PRG_ETH0_TXDLY_SHIFT 5
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#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
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/* divider for the result of m250_sel */
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#define PRG_ETH0_CLK_M250_DIV_SHIFT 7
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#define PRG_ETH0_CLK_M250_DIV_WIDTH 3
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#define PRG_ETH0_RGMII_TX_CLK_EN 10
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#define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
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#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
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#define MUX_CLK_NUM_PARENTS 2
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struct meson8b_dwmac {
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struct platform_device *pdev;
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void __iomem *regs;
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phy_interface_t phy_mode;
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struct clk_mux m250_mux;
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struct clk *m250_mux_clk;
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struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS];
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struct clk_divider m250_div;
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struct clk *m250_div_clk;
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struct clk_fixed_factor fixed_div2;
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struct clk *fixed_div2_clk;
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struct clk_gate rgmii_tx_en;
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struct clk *rgmii_tx_en_clk;
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u32 tx_delay_ns;
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};
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static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
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u32 mask, u32 value)
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{
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u32 data;
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data = readl(dwmac->regs + reg);
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data &= ~mask;
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data |= (value & mask);
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writel(data, dwmac->regs + reg);
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}
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static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
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{
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struct clk_init_data init;
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int i, ret;
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struct device *dev = &dwmac->pdev->dev;
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char clk_name[32];
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const char *clk_div_parents[1];
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const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
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/* get the mux parents from DT */
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for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
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char name[16];
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snprintf(name, sizeof(name), "clkin%d", i);
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dwmac->m250_mux_parent[i] = devm_clk_get(dev, name);
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if (IS_ERR(dwmac->m250_mux_parent[i])) {
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ret = PTR_ERR(dwmac->m250_mux_parent[i]);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Missing clock %s\n", name);
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return ret;
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}
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mux_parent_names[i] =
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__clk_get_name(dwmac->m250_mux_parent[i]);
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}
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/* create the m250_mux */
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snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev));
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init.name = clk_name;
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init.ops = &clk_mux_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = mux_parent_names;
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init.num_parents = MUX_CLK_NUM_PARENTS;
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dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0;
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dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
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dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
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dwmac->m250_mux.flags = 0;
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dwmac->m250_mux.table = NULL;
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dwmac->m250_mux.hw.init = &init;
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dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw);
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if (WARN_ON(IS_ERR(dwmac->m250_mux_clk)))
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return PTR_ERR(dwmac->m250_mux_clk);
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/* create the m250_div */
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snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev));
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init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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dwmac->m250_div.reg = dwmac->regs + PRG_ETH0;
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dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
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dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
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dwmac->m250_div.hw.init = &init;
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dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO |
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CLK_DIVIDER_ROUND_CLOSEST;
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dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw);
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if (WARN_ON(IS_ERR(dwmac->m250_div_clk)))
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return PTR_ERR(dwmac->m250_div_clk);
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/* create the fixed_div2 */
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snprintf(clk_name, sizeof(clk_name), "%s#fixed_div2", dev_name(dev));
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init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
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init.ops = &clk_fixed_factor_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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dwmac->fixed_div2.mult = 1;
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dwmac->fixed_div2.div = 2;
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dwmac->fixed_div2.hw.init = &init;
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dwmac->fixed_div2_clk = devm_clk_register(dev, &dwmac->fixed_div2.hw);
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if (WARN_ON(IS_ERR(dwmac->fixed_div2_clk)))
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return PTR_ERR(dwmac->fixed_div2_clk);
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/* create the rgmii_tx_en */
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init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#rgmii_tx_en",
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dev_name(dev));
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init.ops = &clk_gate_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_div_parents[0] = __clk_get_name(dwmac->fixed_div2_clk);
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init.parent_names = clk_div_parents;
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init.num_parents = ARRAY_SIZE(clk_div_parents);
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dwmac->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
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dwmac->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
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dwmac->rgmii_tx_en.hw.init = &init;
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dwmac->rgmii_tx_en_clk = devm_clk_register(dev,
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&dwmac->rgmii_tx_en.hw);
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if (WARN_ON(IS_ERR(dwmac->rgmii_tx_en_clk)))
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return PTR_ERR(dwmac->rgmii_tx_en_clk);
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return 0;
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}
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static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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{
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int ret;
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u8 tx_dly_val = 0;
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switch (dwmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where
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* 8ns are exactly one cycle of the 125MHz RGMII TX clock):
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* 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
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*/
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tx_dly_val = dwmac->tx_delay_ns >> 1;
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/* fall through */
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* enable RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
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PRG_ETH0_RGMII_MODE);
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/* only relevant for RMII mode -> disable in RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_INVERTED_RMII_CLK, 0);
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
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tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
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/* Configure the 125MHz RGMII TX clock, the IP block changes
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* the output automatically (= without us having to configure
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* a register) based on the line-speed (125MHz for Gbit speeds,
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* 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s).
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*/
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ret = clk_set_rate(dwmac->rgmii_tx_en_clk, 125 * 1000 * 1000);
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if (ret) {
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dev_err(&dwmac->pdev->dev,
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"failed to set RGMII TX clock\n");
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return ret;
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}
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ret = clk_prepare_enable(dwmac->rgmii_tx_en_clk);
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if (ret) {
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dev_err(&dwmac->pdev->dev,
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"failed to enable the RGMII TX clock\n");
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return ret;
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}
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* disable RGMII mode -> enables RMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
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0);
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/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_INVERTED_RMII_CLK,
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PRG_ETH0_INVERTED_RMII_CLK);
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/* TX clock delay cannot be configured in RMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
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0);
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break;
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default:
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dev_err(&dwmac->pdev->dev, "unsupported phy-mode %s\n",
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phy_modes(dwmac->phy_mode));
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return -EINVAL;
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}
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/* enable TX_CLK and PHY_REF_CLK generator */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
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PRG_ETH0_TX_AND_PHY_REF_CLK);
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return 0;
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}
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static int meson8b_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct resource *res;
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struct meson8b_dwmac *dwmac;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac) {
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ret = -ENOMEM;
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goto err_remove_config_dt;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dwmac->regs)) {
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ret = PTR_ERR(dwmac->regs);
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goto err_remove_config_dt;
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}
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dwmac->pdev = pdev;
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dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
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if (dwmac->phy_mode < 0) {
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dev_err(&pdev->dev, "missing phy-mode property\n");
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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/* use 2ns as fallback since this value was previously hardcoded */
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if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
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&dwmac->tx_delay_ns))
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dwmac->tx_delay_ns = 2;
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ret = meson8b_init_rgmii_tx_clk(dwmac);
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if (ret)
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goto err_remove_config_dt;
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ret = meson8b_init_prg_eth(dwmac);
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if (ret)
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goto err_remove_config_dt;
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plat_dat->bsp_priv = dwmac;
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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goto err_clk_disable;
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return 0;
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err_clk_disable:
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->rgmii_tx_en_clk);
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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return ret;
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}
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static int meson8b_dwmac_remove(struct platform_device *pdev)
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{
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struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
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clk_disable_unprepare(dwmac->rgmii_tx_en_clk);
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return stmmac_pltfr_remove(pdev);
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}
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static const struct of_device_id meson8b_dwmac_match[] = {
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{ .compatible = "amlogic,meson8b-dwmac" },
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{ .compatible = "amlogic,meson-gxbb-dwmac" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
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static struct platform_driver meson8b_dwmac_driver = {
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.probe = meson8b_dwmac_probe,
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.remove = meson8b_dwmac_remove,
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.driver = {
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.name = "meson8b-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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.of_match_table = meson8b_dwmac_match,
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},
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};
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module_platform_driver(meson8b_dwmac_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Amlogic Meson8b and GXBB DWMAC glue layer");
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MODULE_LICENSE("GPL v2");
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