mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
cad6fade6e
WSR and RSR are too generic and collide with other macro definitions in the kernel causing warnings in allmodconfig builds. Drop WSR and RSR macros and WSR_* and RSR_* variants. Change get_sr and set_sr to xtensa_get_sr and xtensa_set_sr. Fix up users. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2013 Tensilica Inc.
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*/
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#ifndef _XTENSA_TIMEX_H
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#define _XTENSA_TIMEX_H
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#include <asm/processor.h>
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#if XCHAL_NUM_TIMERS > 0 && \
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XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# define LINUX_TIMER 0
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# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
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#elif XCHAL_NUM_TIMERS > 1 && \
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XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# define LINUX_TIMER 1
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# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
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#elif XCHAL_NUM_TIMERS > 2 && \
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XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# define LINUX_TIMER 2
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# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
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#else
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# error "Bad timer number for Linux configurations!"
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#endif
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extern unsigned long ccount_freq;
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typedef unsigned long long cycles_t;
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#define get_cycles() (0)
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void local_timer_setup(unsigned cpu);
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/*
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* Register access.
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*/
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static inline unsigned long get_ccount (void)
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{
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return xtensa_get_sr(ccount);
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}
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static inline void set_ccount (unsigned long ccount)
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{
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xtensa_set_sr(ccount, ccount);
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}
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static inline unsigned long get_linux_timer (void)
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{
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return xtensa_get_sr(SREG_CCOMPARE + LINUX_TIMER);
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}
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static inline void set_linux_timer (unsigned long ccompare)
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{
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xtensa_set_sr(ccompare, SREG_CCOMPARE + LINUX_TIMER);
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}
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#endif /* _XTENSA_TIMEX_H */
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