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fec3259c9f
Cache invalidation macros use cache line size to iterate over invalidated cache lines, assuming that all cache ways are invalidated by single instruction, but xtensa ISA recommends to not assume that for future compatibility: In some implementations all ways at index Addry-1..z are invalidated regardless of the specified way, but for future compatibility this behavior should not be assumed. Iterate over all cache ways in ___invalidate_icache_all and ___invalidate_dcache_all. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
215 lines
3.8 KiB
C
215 lines
3.8 KiB
C
/*
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* include/asm-xtensa/cacheasm.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Tensilica Inc.
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*/
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#include <asm/cache.h>
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#include <asm/asmmacro.h>
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#include <linux/stringify.h>
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/*
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* Define cache functions as macros here so that they can be used
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* by the kernel and boot loader. We should consider moving them to a
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* library that can be linked by both.
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*
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* Locking
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*
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* ___unlock_dcache_all
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* ___unlock_icache_all
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*
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* Flush and invaldating
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*
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* ___flush_invalidate_dcache_{all|range|page}
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* ___flush_dcache_{all|range|page}
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* ___invalidate_dcache_{all|range|page}
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* ___invalidate_icache_{all|range|page}
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*
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*/
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.macro __loop_cache_unroll ar at insn size line_width max_immed
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.if (1 << (\line_width)) > (\max_immed)
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.set _reps, 1
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.elseif (2 << (\line_width)) > (\max_immed)
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.set _reps, 2
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.else
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.set _reps, 4
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.endif
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__loopi \ar, \at, \size, (_reps << (\line_width))
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.set _index, 0
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.rep _reps
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\insn \ar, _index << (\line_width)
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.set _index, _index + 1
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.endr
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__endla \ar, \at, _reps << (\line_width)
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.endm
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.macro __loop_cache_all ar at insn size line_width max_immed
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movi \ar, 0
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__loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed
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.endm
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.macro __loop_cache_range ar as at insn line_width
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extui \at, \ar, 0, \line_width
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add \as, \as, \at
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__loops \ar, \as, \at, \line_width
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\insn \ar, 0
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__endla \ar, \at, (1 << (\line_width))
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.endm
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.macro __loop_cache_page ar at insn line_width max_immed
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__loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed
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.endm
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.macro ___unlock_dcache_all ar at
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#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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.macro ___unlock_icache_all ar at
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#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
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XCHAL_ICACHE_LINEWIDTH 240
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#endif
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.endm
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.macro ___flush_invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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.macro ___flush_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 240
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#endif
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.endm
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.macro ___invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
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XCHAL_DCACHE_LINEWIDTH 1020
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#endif
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.endm
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.macro ___invalidate_icache_all ar at
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#if XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
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XCHAL_ICACHE_LINEWIDTH 1020
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#endif
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.endm
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.macro ___flush_invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_icache_range ar as at
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#if XCHAL_ICACHE_SIZE
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__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
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#endif
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.endm
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.macro ___flush_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
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#endif
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.endm
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.macro ___invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
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#endif
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.endm
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.macro ___invalidate_icache_page ar as
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#if XCHAL_ICACHE_SIZE
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__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
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#endif
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.endm
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