mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 06:16:46 +07:00
93e2ca0285
This is needed for supporting ultra high speed cards like SD3.0 cards. Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
105 lines
2.2 KiB
Plaintext
105 lines
2.2 KiB
Plaintext
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/ {
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memory {
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reg = <0x10000000 0x80000000>;
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};
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio3 19 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
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status = "disabled"; /* pin conflict with WEIM NOR */
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_2>;
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phy-mode = "rgmii";
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
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MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
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MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
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>;
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};
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};
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ecspi1 {
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pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
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fsl,pins = <
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MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
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>;
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};
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};
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4_1>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3_1>;
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pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
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cd-gpios = <&gpio6 15 0>;
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wp-gpios = <&gpio1 13 0>;
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status = "okay";
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};
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&weim {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>;
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status = "disabled"; /* pin conflict with SPI NOR */
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <2>;
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fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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