mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
aebf052bb6
We originally added support, in some cases partial, for different modes of operations via guc clients: - proxy vs direct submission; - variable engine mask per-client. We only ever used one flow (all submissions via a single proxy), so the other code paths haven't been exercised and are most likely non-functional. The guc firmware interface is also in the process of being updated to better fit the i915 flow and our client abstraction will need to change accordingly (or possibly go away entirely), so these old unused paths can be considered dead and removed. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Acked-by: Matthew Brost <Matthew Brost <matthew.brost@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190710005437.3496-3-daniele.ceraolospurio@intel.com
88 lines
3.4 KiB
C
88 lines
3.4 KiB
C
/*
|
|
* Copyright © 2014-2017 Intel Corporation
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
* IN THE SOFTWARE.
|
|
*
|
|
*/
|
|
|
|
#ifndef _INTEL_GUC_SUBMISSION_H_
|
|
#define _INTEL_GUC_SUBMISSION_H_
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include "gt/intel_engine_types.h"
|
|
|
|
#include "i915_gem.h"
|
|
#include "i915_selftest.h"
|
|
|
|
struct drm_i915_private;
|
|
|
|
/*
|
|
* This structure primarily describes the GEM object shared with the GuC.
|
|
* The specs sometimes refer to this object as a "GuC context", but we use
|
|
* the term "client" to avoid confusion with hardware contexts. This
|
|
* GEM object is held for the entire lifetime of our interaction with
|
|
* the GuC, being allocated before the GuC is loaded with its firmware.
|
|
* Because there's no way to update the address used by the GuC after
|
|
* initialisation, the shared object must stay pinned into the GGTT as
|
|
* long as the GuC is in use. We also keep the first page (only) mapped
|
|
* into kernel address space, as it includes shared data that must be
|
|
* updated on every request submission.
|
|
*
|
|
* The single GEM object described here is actually made up of several
|
|
* separate areas, as far as the GuC is concerned. The first page (kept
|
|
* kmap'd) includes the "process descriptor" which holds sequence data for
|
|
* the doorbell, and one cacheline which actually *is* the doorbell; a
|
|
* write to this will "ring the doorbell" (i.e. send an interrupt to the
|
|
* GuC). The subsequent pages of the client object constitute the work
|
|
* queue (a circular array of work items), again described in the process
|
|
* descriptor. Work queue pages are mapped momentarily as required.
|
|
*/
|
|
struct intel_guc_client {
|
|
struct i915_vma *vma;
|
|
void *vaddr;
|
|
struct intel_guc *guc;
|
|
|
|
/* bitmap of (host) engine ids */
|
|
u32 priority;
|
|
u32 stage_id;
|
|
u32 proc_desc_offset;
|
|
|
|
u16 doorbell_id;
|
|
unsigned long doorbell_offset;
|
|
|
|
/* Protects GuC client's WQ access */
|
|
spinlock_t wq_lock;
|
|
/* Per-engine counts of GuC submissions */
|
|
u64 submissions[I915_NUM_ENGINES];
|
|
|
|
/* For testing purposes, use nop WQ items instead of real ones */
|
|
I915_SELFTEST_DECLARE(bool use_nop_wqi);
|
|
};
|
|
|
|
int intel_guc_submission_init(struct intel_guc *guc);
|
|
int intel_guc_submission_enable(struct intel_guc *guc);
|
|
void intel_guc_submission_disable(struct intel_guc *guc);
|
|
void intel_guc_submission_fini(struct intel_guc *guc);
|
|
int intel_guc_preempt_work_create(struct intel_guc *guc);
|
|
void intel_guc_preempt_work_destroy(struct intel_guc *guc);
|
|
|
|
#endif
|