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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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25aee3debe
The remaining dvb drivers are pci, so rename them to match the bus. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
152 lines
5.3 KiB
C
152 lines
5.3 KiB
C
/*
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* ddbridge-regs.h: Digital Devices PCIe bridge driver
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*
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* Copyright (C) 2010-2011 Digital Devices GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*/
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/* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */
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/* Register Definitions */
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#define CUR_REGISTERMAP_VERSION 0x10000
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#define HARDWARE_VERSION 0x00
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#define REGISTERMAP_VERSION 0x04
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/* ------------------------------------------------------------------------- */
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/* SPI Controller */
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#define SPI_CONTROL 0x10
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#define SPI_DATA 0x14
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/* ------------------------------------------------------------------------- */
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/* Interrupt controller */
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/* How many MSI's are available depends on HW (Min 2 max 8) */
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/* How many are usable also depends on Host platform */
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#define INTERRUPT_BASE (0x40)
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#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
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#define MSI0_ENABLE (INTERRUPT_BASE + 0x00)
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#define MSI1_ENABLE (INTERRUPT_BASE + 0x04)
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#define MSI2_ENABLE (INTERRUPT_BASE + 0x08)
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#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C)
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#define MSI4_ENABLE (INTERRUPT_BASE + 0x10)
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#define MSI5_ENABLE (INTERRUPT_BASE + 0x14)
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#define MSI6_ENABLE (INTERRUPT_BASE + 0x18)
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#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C)
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#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
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#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
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#define INTMASK_I2C1 (0x00000001)
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#define INTMASK_I2C2 (0x00000002)
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#define INTMASK_I2C3 (0x00000004)
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#define INTMASK_I2C4 (0x00000008)
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#define INTMASK_CIRQ1 (0x00000010)
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#define INTMASK_CIRQ2 (0x00000020)
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#define INTMASK_CIRQ3 (0x00000040)
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#define INTMASK_CIRQ4 (0x00000080)
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#define INTMASK_TSINPUT1 (0x00000100)
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#define INTMASK_TSINPUT2 (0x00000200)
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#define INTMASK_TSINPUT3 (0x00000400)
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#define INTMASK_TSINPUT4 (0x00000800)
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#define INTMASK_TSINPUT5 (0x00001000)
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#define INTMASK_TSINPUT6 (0x00002000)
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#define INTMASK_TSINPUT7 (0x00004000)
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#define INTMASK_TSINPUT8 (0x00008000)
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#define INTMASK_TSOUTPUT1 (0x00010000)
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#define INTMASK_TSOUTPUT2 (0x00020000)
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#define INTMASK_TSOUTPUT3 (0x00040000)
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#define INTMASK_TSOUTPUT4 (0x00080000)
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/* ------------------------------------------------------------------------- */
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/* I2C Master Controller */
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#define I2C_BASE (0x80) /* Byte offset */
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#define I2C_COMMAND (0x00)
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#define I2C_TIMING (0x04)
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#define I2C_TASKLENGTH (0x08) /* High read, low write */
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#define I2C_TASKADDRESS (0x0C) /* High read, low write */
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#define I2C_MONITOR (0x1C)
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#define I2C_BASE_1 (I2C_BASE + 0x00)
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#define I2C_BASE_2 (I2C_BASE + 0x20)
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#define I2C_BASE_3 (I2C_BASE + 0x40)
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#define I2C_BASE_4 (I2C_BASE + 0x60)
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#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20)
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#define I2C_TASKMEM_BASE (0x1000) /* Byte offset */
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#define I2C_TASKMEM_SIZE (0x1000)
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#define I2C_SPEED_400 (0x04030404)
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#define I2C_SPEED_200 (0x09080909)
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#define I2C_SPEED_154 (0x0C0B0C0C)
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#define I2C_SPEED_100 (0x13121313)
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#define I2C_SPEED_77 (0x19181919)
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#define I2C_SPEED_50 (0x27262727)
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/* ------------------------------------------------------------------------- */
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/* DMA Controller */
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#define DMA_BASE_WRITE (0x100)
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#define DMA_BASE_READ (0x140)
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#define DMA_CONTROL (0x00) /* 64 */
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#define DMA_ERROR (0x04) /* 65 ( only read instance ) */
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#define DMA_DIAG_CONTROL (0x1C) /* 71 */
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#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */
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#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */
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#define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */
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#define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */
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#define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */
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#define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */
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#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */
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#define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */
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/* ------------------------------------------------------------------------- */
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/* DMA Buffer */
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#define TS_INPUT_BASE (0x200)
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#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00)
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#define TS_OUTPUT_BASE (0x280)
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#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00)
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#define DMA_BUFFER_BASE (0x300)
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#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 16 + 0x00)
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#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 16 + 0x04)
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#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 16 + 0x08)
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#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 16 + 0x0c)
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#define DMA_BASE_ADDRESS_TABLE (0x2000)
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#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512)
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