mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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27b67278e0
This reworks the MMU handling to make it possible to have multiple MMU contexts. A context is basically one instance of GPU page tables. Currently we have one set of page tables per GPU, which isn't all that clever, as it has the following two consequences: 1. All GPU clients (aka processes) are sharing the same pagetables, which means there is no isolation between clients, but only between GPU assigned memory spaces and the rest of the system. Better than nothing, but also not great. 2. Clients operating on the same set of buffers with different etnaviv GPU cores, e.g. a workload using both the 2D and 3D GPU, need to map the used buffers into the pagetable sets of each used GPU. This patch reworks all the MMU handling to introduce the abstraction of the MMU context. A context can be shared across different GPU cores, as long as they have compatible MMU implementations, which is the case for all systems with Vivante GPUs seen in the wild. As MMUv1 is not able to change pagetables on the fly, without a "stop the world" operation, which stops GPU, changes pagetables via CPU interaction, restarts GPU, the implementation introduces a shared context on MMUv1, which is returned whenever there is a request for a new context. This patch assigns a MMU context to each GPU, so on MMUv2 systems there is still one set of pagetables per GPU, but due to the shared context MMUv1 systems see a change in behavior as now a single pagetable set is used across all GPU cores. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Guido Günther <agx@sigxcpu.org>
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015-2018 Etnaviv Project
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*/
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#ifndef __ETNAVIV_MMU_H__
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#define __ETNAVIV_MMU_H__
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#define ETNAVIV_PROT_READ (1 << 0)
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#define ETNAVIV_PROT_WRITE (1 << 1)
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enum etnaviv_iommu_version {
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ETNAVIV_IOMMU_V1 = 0,
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ETNAVIV_IOMMU_V2,
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};
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struct etnaviv_gpu;
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struct etnaviv_vram_mapping;
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struct etnaviv_iommu_global;
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struct etnaviv_iommu_context;
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struct etnaviv_iommu_ops {
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struct etnaviv_iommu_context *(*init)(struct etnaviv_iommu_global *);
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void (*free)(struct etnaviv_iommu_context *);
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int (*map)(struct etnaviv_iommu_context *context, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot);
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size_t (*unmap)(struct etnaviv_iommu_context *context, unsigned long iova,
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size_t size);
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size_t (*dump_size)(struct etnaviv_iommu_context *);
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void (*dump)(struct etnaviv_iommu_context *, void *);
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void (*restore)(struct etnaviv_gpu *, struct etnaviv_iommu_context *);
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};
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extern const struct etnaviv_iommu_ops etnaviv_iommuv1_ops;
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extern const struct etnaviv_iommu_ops etnaviv_iommuv2_ops;
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#define ETNAVIV_PTA_SIZE SZ_4K
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#define ETNAVIV_PTA_ENTRIES (ETNAVIV_PTA_SIZE / sizeof(u64))
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struct etnaviv_iommu_global {
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struct device *dev;
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enum etnaviv_iommu_version version;
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const struct etnaviv_iommu_ops *ops;
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unsigned int use;
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struct mutex lock;
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void *bad_page_cpu;
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dma_addr_t bad_page_dma;
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/*
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* This union holds members needed by either MMUv1 or MMUv2, which
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* can not exist at the same time.
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*/
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union {
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struct {
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struct etnaviv_iommu_context *shared_context;
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} v1;
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struct {
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/* P(age) T(able) A(rray) */
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u64 *pta_cpu;
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dma_addr_t pta_dma;
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struct spinlock pta_lock;
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DECLARE_BITMAP(pta_alloc, ETNAVIV_PTA_ENTRIES);
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} v2;
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};
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};
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struct etnaviv_iommu_context {
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struct kref refcount;
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struct etnaviv_iommu_global *global;
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/* memory manager for GPU address area */
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struct mutex lock;
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struct list_head mappings;
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struct drm_mm mm;
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unsigned int flush_seq;
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};
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int etnaviv_iommu_global_init(struct etnaviv_gpu *gpu);
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void etnaviv_iommu_global_fini(struct etnaviv_gpu *gpu);
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struct etnaviv_gem_object;
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int etnaviv_iommu_map_gem(struct etnaviv_iommu_context *context,
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struct etnaviv_gem_object *etnaviv_obj, u32 memory_base,
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struct etnaviv_vram_mapping *mapping);
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void etnaviv_iommu_unmap_gem(struct etnaviv_iommu_context *context,
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struct etnaviv_vram_mapping *mapping);
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int etnaviv_iommu_get_suballoc_va(struct etnaviv_iommu_context *ctx,
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struct etnaviv_vram_mapping *mapping,
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u32 memory_base, dma_addr_t paddr,
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size_t size);
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void etnaviv_iommu_put_suballoc_va(struct etnaviv_iommu_context *ctx,
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struct etnaviv_vram_mapping *mapping);
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size_t etnaviv_iommu_dump_size(struct etnaviv_iommu_context *ctx);
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void etnaviv_iommu_dump(struct etnaviv_iommu_context *ctx, void *buf);
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struct etnaviv_iommu_context *
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etnaviv_iommu_context_init(struct etnaviv_iommu_global *global);
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static inline void etnaviv_iommu_context_get(struct etnaviv_iommu_context *ctx)
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{
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kref_get(&ctx->refcount);
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}
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void etnaviv_iommu_context_put(struct etnaviv_iommu_context *ctx);
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void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
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struct etnaviv_iommu_context *ctx);
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struct etnaviv_iommu_context *
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etnaviv_iommuv1_context_alloc(struct etnaviv_iommu_global *global);
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struct etnaviv_iommu_context *
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etnaviv_iommuv2_context_alloc(struct etnaviv_iommu_global *global);
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#endif /* __ETNAVIV_MMU_H__ */
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