mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 13:53:51 +07:00
d792bc77e5
The DE signal is currently configured to be identical to the DISP signal and is used for the same purpose. To make it clearer that the DISP pin outputs the DISP signal, select it explicitly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
667 lines
18 KiB
C
667 lines
18 KiB
C
/*
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* rcar_du_crtc.c -- R-Car Display Unit CRTCs
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "rcar_du_crtc.h"
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#include "rcar_du_drv.h"
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#include "rcar_du_kms.h"
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#include "rcar_du_plane.h"
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#include "rcar_du_regs.h"
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#include "rcar_du_vsp.h"
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static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
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}
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static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
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}
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static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
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rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
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}
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static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
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rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
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}
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static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
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u32 clr, u32 set)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
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}
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static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
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{
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int ret;
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ret = clk_prepare_enable(rcrtc->clock);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(rcrtc->extclock);
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if (ret < 0)
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goto error_clock;
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ret = rcar_du_group_get(rcrtc->group);
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if (ret < 0)
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goto error_group;
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return 0;
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error_group:
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clk_disable_unprepare(rcrtc->extclock);
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error_clock:
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clk_disable_unprepare(rcrtc->clock);
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return ret;
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}
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static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
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{
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rcar_du_group_put(rcrtc->group);
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clk_disable_unprepare(rcrtc->extclock);
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clk_disable_unprepare(rcrtc->clock);
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}
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/* -----------------------------------------------------------------------------
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* Hardware Setup
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*/
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static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
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unsigned long mode_clock = mode->clock * 1000;
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unsigned long clk;
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u32 value;
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u32 escr;
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u32 div;
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/* Compute the clock divisor and select the internal or external dot
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* clock based on the requested frequency.
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*/
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clk = clk_get_rate(rcrtc->clock);
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div = DIV_ROUND_CLOSEST(clk, mode_clock);
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div = clamp(div, 1U, 64U) - 1;
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escr = div | ESCR_DCLKSEL_CLKS;
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if (rcrtc->extclock) {
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unsigned long extclk;
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unsigned long extrate;
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unsigned long rate;
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u32 extdiv;
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extclk = clk_get_rate(rcrtc->extclock);
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extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
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extdiv = clamp(extdiv, 1U, 64U) - 1;
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rate = clk / (div + 1);
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extrate = extclk / (extdiv + 1);
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if (abs((long)extrate - (long)mode_clock) <
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abs((long)rate - (long)mode_clock)) {
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dev_dbg(rcrtc->group->dev->dev,
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"crtc%u: using external clock\n", rcrtc->index);
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escr = extdiv | ESCR_DCLKSEL_DCLKIN;
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}
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}
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
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escr);
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
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/* Signal polarities */
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value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
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| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
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| DSMR_DIPM_DISP | DSMR_CSPM;
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rcar_du_crtc_write(rcrtc, DSMR, value);
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/* Display timings */
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rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
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rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
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mode->hdisplay - 19);
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rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
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mode->hsync_start - 1);
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rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
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rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
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mode->crtc_vsync_end - 2);
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rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
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mode->crtc_vsync_end +
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mode->crtc_vdisplay - 2);
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rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
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mode->crtc_vsync_end +
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mode->crtc_vsync_start - 1);
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rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
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rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
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rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
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}
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void rcar_du_crtc_route_output(struct drm_crtc *crtc,
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enum rcar_du_output output)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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/* Store the route from the CRTC output to the DU output. The DU will be
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* configured when starting the CRTC.
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*/
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rcrtc->outputs |= BIT(output);
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/* Store RGB routing to DPAD0, the hardware will be configured when
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* starting the CRTC.
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*/
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if (output == RCAR_DU_OUTPUT_DPAD0)
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rcdu->dpad0_source = rcrtc->index;
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}
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static unsigned int plane_zpos(struct rcar_du_plane *plane)
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{
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return to_rcar_plane_state(plane->plane.state)->zpos;
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}
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static const struct rcar_du_format_info *
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plane_format(struct rcar_du_plane *plane)
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{
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return to_rcar_plane_state(plane->plane.state)->format;
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}
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static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
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{
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struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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unsigned int num_planes = 0;
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unsigned int dptsr_planes;
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unsigned int hwplanes = 0;
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unsigned int prio = 0;
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unsigned int i;
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u32 dspr = 0;
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for (i = 0; i < rcrtc->group->num_planes; ++i) {
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struct rcar_du_plane *plane = &rcrtc->group->planes[i];
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unsigned int j;
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if (plane->plane.state->crtc != &rcrtc->crtc)
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continue;
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/* Insert the plane in the sorted planes array. */
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for (j = num_planes++; j > 0; --j) {
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if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
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break;
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planes[j] = planes[j-1];
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}
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planes[j] = plane;
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prio += plane_format(plane)->planes * 4;
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}
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for (i = 0; i < num_planes; ++i) {
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struct rcar_du_plane *plane = planes[i];
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struct drm_plane_state *state = plane->plane.state;
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unsigned int index = to_rcar_plane_state(state)->hwindex;
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prio -= 4;
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dspr |= (index + 1) << prio;
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hwplanes |= 1 << index;
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if (plane_format(plane)->planes == 2) {
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index = (index + 1) % 8;
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prio -= 4;
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dspr |= (index + 1) << prio;
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hwplanes |= 1 << index;
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}
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}
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/* If VSP+DU integration is enabled the plane assignment is fixed. */
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if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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dspr = (rcrtc->index % 2) + 1;
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hwplanes = 1 << (rcrtc->index % 2);
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}
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/* Update the planes to display timing and dot clock generator
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* associations.
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*
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* Updating the DPTSR register requires restarting the CRTC group,
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* resulting in visible flicker. To mitigate the issue only update the
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* association if needed by enabled planes. Planes being disabled will
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* keep their current association.
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*/
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mutex_lock(&rcrtc->group->lock);
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dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
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: rcrtc->group->dptsr_planes & ~hwplanes;
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if (dptsr_planes != rcrtc->group->dptsr_planes) {
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rcar_du_group_write(rcrtc->group, DPTSR,
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(dptsr_planes << 16) | dptsr_planes);
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rcrtc->group->dptsr_planes = dptsr_planes;
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if (rcrtc->group->used_crtcs)
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rcar_du_group_restart(rcrtc->group);
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}
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/* Restart the group if plane sources have changed. */
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if (rcrtc->group->need_restart)
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rcar_du_group_restart(rcrtc->group);
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mutex_unlock(&rcrtc->group->lock);
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
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dspr);
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}
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/* -----------------------------------------------------------------------------
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* Page Flip
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*/
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static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
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{
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struct drm_pending_vblank_event *event;
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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event = rcrtc->event;
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rcrtc->event = NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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if (event == NULL)
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return;
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spin_lock_irqsave(&dev->event_lock, flags);
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drm_send_vblank_event(dev, rcrtc->index, event);
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wake_up(&rcrtc->flip_wait);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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drm_crtc_vblank_put(&rcrtc->crtc);
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}
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static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
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{
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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bool pending;
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spin_lock_irqsave(&dev->event_lock, flags);
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pending = rcrtc->event != NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return pending;
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}
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static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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if (wait_event_timeout(rcrtc->flip_wait,
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!rcar_du_crtc_page_flip_pending(rcrtc),
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msecs_to_jiffies(50)))
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return;
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dev_warn(rcdu->dev, "page flip timeout\n");
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rcar_du_crtc_finish_page_flip(rcrtc);
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}
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/* -----------------------------------------------------------------------------
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* Start/Stop and Suspend/Resume
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*/
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static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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bool interlaced;
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if (rcrtc->started)
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return;
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/* Set display off and background to black */
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rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
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rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
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/* Configure display timings and output routing */
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rcar_du_crtc_set_display_timing(rcrtc);
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rcar_du_group_set_routing(rcrtc->group);
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/* Start with all planes disabled. */
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
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/* Select master sync mode. This enables display operation in master
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* sync mode (with the HSYNC and VSYNC signals configured as outputs and
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* actively driven).
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*/
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interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
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rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
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(interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
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DSYSR_TVM_MASTER);
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rcar_du_group_start_stop(rcrtc->group, true);
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/* Enable the VSP compositor. */
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if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
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rcar_du_vsp_enable(rcrtc);
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/* Turn vertical blanking interrupt reporting back on. */
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drm_crtc_vblank_on(crtc);
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rcrtc->started = true;
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}
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static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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if (!rcrtc->started)
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return;
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/* Disable all planes and wait for the change to take effect. This is
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* required as the DSnPR registers are updated on vblank, and no vblank
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* will occur once the CRTC is stopped. Disabling planes when starting
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* the CRTC thus wouldn't be enough as it would start scanning out
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* immediately from old frame buffers until the next vblank.
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*
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* This increases the CRTC stop delay, especially when multiple CRTCs
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* are stopped in one operation as we now wait for one vblank per CRTC.
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* Whether this can be improved needs to be researched.
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*/
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
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drm_crtc_wait_one_vblank(crtc);
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/* Disable vertical blanking interrupt reporting. We first need to wait
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* for page flip completion before stopping the CRTC as userspace
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* expects page flips to eventually complete.
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*/
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rcar_du_crtc_wait_page_flip(rcrtc);
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drm_crtc_vblank_off(crtc);
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/* Disable the VSP compositor. */
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if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
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rcar_du_vsp_disable(rcrtc);
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/* Select switch sync mode. This stops display operation and configures
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* the HSYNC and VSYNC signals as inputs.
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*/
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rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
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rcar_du_group_start_stop(rcrtc->group, false);
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rcrtc->started = false;
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}
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void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
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{
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if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
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rcar_du_vsp_disable(rcrtc);
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rcar_du_crtc_stop(rcrtc);
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rcar_du_crtc_put(rcrtc);
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}
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void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
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{
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unsigned int i;
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if (!rcrtc->crtc.state->active)
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return;
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rcar_du_crtc_get(rcrtc);
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rcar_du_crtc_start(rcrtc);
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/* Commit the planes state. */
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if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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rcar_du_vsp_enable(rcrtc);
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} else {
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for (i = 0; i < rcrtc->group->num_planes; ++i) {
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struct rcar_du_plane *plane = &rcrtc->group->planes[i];
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if (plane->plane.state->crtc != &rcrtc->crtc)
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continue;
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rcar_du_plane_setup(plane);
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}
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}
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rcar_du_crtc_update_planes(rcrtc);
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}
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/* -----------------------------------------------------------------------------
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* CRTC Functions
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*/
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static void rcar_du_crtc_enable(struct drm_crtc *crtc)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
|
|
|
rcar_du_crtc_get(rcrtc);
|
|
rcar_du_crtc_start(rcrtc);
|
|
}
|
|
|
|
static void rcar_du_crtc_disable(struct drm_crtc *crtc)
|
|
{
|
|
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
|
|
|
rcar_du_crtc_stop(rcrtc);
|
|
rcar_du_crtc_put(rcrtc);
|
|
|
|
rcrtc->outputs = 0;
|
|
}
|
|
|
|
static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
/* TODO Fixup modes */
|
|
return true;
|
|
}
|
|
|
|
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_crtc_state)
|
|
{
|
|
struct drm_pending_vblank_event *event = crtc->state->event;
|
|
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
|
struct drm_device *dev = rcrtc->crtc.dev;
|
|
unsigned long flags;
|
|
|
|
if (event) {
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
rcrtc->event = event;
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
}
|
|
|
|
if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
|
|
rcar_du_vsp_atomic_begin(rcrtc);
|
|
}
|
|
|
|
static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_crtc_state)
|
|
{
|
|
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
|
|
|
rcar_du_crtc_update_planes(rcrtc);
|
|
|
|
if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
|
|
rcar_du_vsp_atomic_flush(rcrtc);
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
|
|
.mode_fixup = rcar_du_crtc_mode_fixup,
|
|
.disable = rcar_du_crtc_disable,
|
|
.enable = rcar_du_crtc_enable,
|
|
.atomic_begin = rcar_du_crtc_atomic_begin,
|
|
.atomic_flush = rcar_du_crtc_atomic_flush,
|
|
};
|
|
|
|
static const struct drm_crtc_funcs crtc_funcs = {
|
|
.reset = drm_atomic_helper_crtc_reset,
|
|
.destroy = drm_crtc_cleanup,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Interrupt Handling
|
|
*/
|
|
|
|
static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
|
|
{
|
|
struct rcar_du_crtc *rcrtc = arg;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 status;
|
|
|
|
status = rcar_du_crtc_read(rcrtc, DSSR);
|
|
rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
|
|
|
|
if (status & DSSR_FRM) {
|
|
drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
|
|
rcar_du_crtc_finish_page_flip(rcrtc);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Initialization
|
|
*/
|
|
|
|
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
|
|
{
|
|
static const unsigned int mmio_offsets[] = {
|
|
DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
|
|
};
|
|
|
|
struct rcar_du_device *rcdu = rgrp->dev;
|
|
struct platform_device *pdev = to_platform_device(rcdu->dev);
|
|
struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
|
|
struct drm_crtc *crtc = &rcrtc->crtc;
|
|
struct drm_plane *primary;
|
|
unsigned int irqflags;
|
|
struct clk *clk;
|
|
char clk_name[9];
|
|
char *name;
|
|
int irq;
|
|
int ret;
|
|
|
|
/* Get the CRTC clock and the optional external clock. */
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
|
|
sprintf(clk_name, "du.%u", index);
|
|
name = clk_name;
|
|
} else {
|
|
name = NULL;
|
|
}
|
|
|
|
rcrtc->clock = devm_clk_get(rcdu->dev, name);
|
|
if (IS_ERR(rcrtc->clock)) {
|
|
dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
|
|
return PTR_ERR(rcrtc->clock);
|
|
}
|
|
|
|
sprintf(clk_name, "dclkin.%u", index);
|
|
clk = devm_clk_get(rcdu->dev, clk_name);
|
|
if (!IS_ERR(clk)) {
|
|
rcrtc->extclock = clk;
|
|
} else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
|
|
dev_info(rcdu->dev, "can't get external clock %u\n", index);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
init_waitqueue_head(&rcrtc->flip_wait);
|
|
|
|
rcrtc->group = rgrp;
|
|
rcrtc->mmio_offset = mmio_offsets[index];
|
|
rcrtc->index = index;
|
|
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
|
|
primary = &rcrtc->vsp->planes[0].plane;
|
|
else
|
|
primary = &rgrp->planes[index % 2].plane;
|
|
|
|
ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary,
|
|
NULL, &crtc_funcs, NULL);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
drm_crtc_helper_add(crtc, &crtc_helper_funcs);
|
|
|
|
/* Start with vertical blanking interrupt reporting disabled. */
|
|
drm_crtc_vblank_off(crtc);
|
|
|
|
/* Register the interrupt handler. */
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
|
|
irq = platform_get_irq(pdev, index);
|
|
irqflags = 0;
|
|
} else {
|
|
irq = platform_get_irq(pdev, 0);
|
|
irqflags = IRQF_SHARED;
|
|
}
|
|
|
|
if (irq < 0) {
|
|
dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
|
|
dev_name(rcdu->dev), rcrtc);
|
|
if (ret < 0) {
|
|
dev_err(rcdu->dev,
|
|
"failed to register IRQ for CRTC %u\n", index);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
|
|
{
|
|
if (enable) {
|
|
rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
|
|
rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
|
|
} else {
|
|
rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
|
|
}
|
|
}
|