mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 01:15:38 +07:00
741deade2a
Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
618 lines
14 KiB
C
618 lines
14 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v3_1.h"
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#include "psp_v10_0.h"
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#include "psp_v11_0.h"
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static void psp_set_funcs(struct amdgpu_device *adev);
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static int psp_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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psp_set_funcs(adev);
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return 0;
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}
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static int psp_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct psp_context *psp = &adev->psp;
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int ret;
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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psp_v3_1_set_psp_funcs(psp);
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break;
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case CHIP_RAVEN:
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psp_v10_0_set_psp_funcs(psp);
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break;
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case CHIP_VEGA20:
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psp_v11_0_set_psp_funcs(psp);
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break;
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default:
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return -EINVAL;
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}
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psp->adev = adev;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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ret = psp_init_microcode(psp);
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if (ret) {
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DRM_ERROR("Failed to load psp firmware!\n");
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return ret;
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}
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return 0;
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}
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static int psp_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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release_firmware(adev->psp.sos_fw);
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adev->psp.sos_fw = NULL;
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release_firmware(adev->psp.asd_fw);
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adev->psp.asd_fw = NULL;
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return 0;
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}
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int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
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uint32_t reg_val, uint32_t mask, bool check_changed)
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{
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uint32_t val;
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int i;
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struct amdgpu_device *adev = psp->adev;
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for (i = 0; i < adev->usec_timeout; i++) {
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val = RREG32(reg_index);
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if (check_changed) {
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if (val != reg_val)
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return 0;
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} else {
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if ((val & mask) == reg_val)
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return 0;
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}
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udelay(1);
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}
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return -ETIME;
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}
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static int
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psp_cmd_submit_buf(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
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int index)
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{
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int ret;
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memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
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memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
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ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
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fence_mc_addr, index);
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while (*((unsigned int *)psp->fence_buf) != index) {
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msleep(1);
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}
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/* the status field must be 0 after FW is loaded */
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if (ucode && psp->cmd_buf_mem->resp.status) {
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DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
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psp->cmd_buf_mem->resp.status, ucode->ucode_id);
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return -EINVAL;
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}
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if (ucode) {
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ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
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ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
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}
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return ret;
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}
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static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
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uint64_t tmr_mc, uint32_t size)
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{
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cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
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cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
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cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
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cmd->cmd.cmd_setup_tmr.buf_size = size;
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}
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/* Set up Trusted Memory Region */
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static int psp_tmr_init(struct psp_context *psp)
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{
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int ret;
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/*
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* Allocate 3M memory aligned to 1M from Frame Buffer (local
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* physical).
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*
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* Note: this memory need be reserved till the driver
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* uninitializes.
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*/
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ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
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AMDGPU_GEM_DOMAIN_VRAM,
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&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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return ret;
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}
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static int psp_tmr_load(struct psp_context *psp)
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{
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int ret;
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struct psp_gfx_cmd_resp *cmd;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
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DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
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PSP_TMR_SIZE, psp->tmr_mc_addr);
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ret = psp_cmd_submit_buf(psp, NULL, cmd,
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psp->fence_buf_mc_addr, 1);
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if (ret)
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goto failed;
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kfree(cmd);
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return 0;
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failed:
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kfree(cmd);
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return ret;
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}
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static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
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uint64_t asd_mc, uint64_t asd_mc_shared,
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uint32_t size, uint32_t shared_size)
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{
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cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
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cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
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cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
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cmd->cmd.cmd_load_ta.app_len = size;
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cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
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cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
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cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
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}
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static int psp_asd_init(struct psp_context *psp)
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{
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int ret;
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/*
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* Allocate 16k memory aligned to 4k from Frame Buffer (local
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* physical) for shared ASD <-> Driver
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*/
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ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
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&psp->asd_shared_bo,
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&psp->asd_shared_mc_addr,
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&psp->asd_shared_buf);
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return ret;
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}
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static int psp_asd_load(struct psp_context *psp)
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{
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int ret;
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struct psp_gfx_cmd_resp *cmd;
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/* If PSP version doesn't match ASD version, asd loading will be failed.
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* add workaround to bypass it for sriov now.
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* TODO: add version check to make it common
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*/
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if (amdgpu_sriov_vf(psp->adev))
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return 0;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!cmd)
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return -ENOMEM;
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memset(psp->fw_pri_buf, 0, PSP_1_MEG);
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memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
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psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
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psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
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ret = psp_cmd_submit_buf(psp, NULL, cmd,
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psp->fence_buf_mc_addr, 2);
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kfree(cmd);
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return ret;
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}
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static int psp_hw_start(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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int ret;
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if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
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ret = psp_bootloader_load_sysdrv(psp);
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if (ret)
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return ret;
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ret = psp_bootloader_load_sos(psp);
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if (ret)
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return ret;
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}
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ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
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if (ret)
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return ret;
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ret = psp_tmr_load(psp);
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if (ret)
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return ret;
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ret = psp_asd_load(psp);
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if (ret)
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return ret;
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return 0;
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}
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static int psp_np_fw_load(struct psp_context *psp)
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{
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int i, ret;
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struct amdgpu_firmware_info *ucode;
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struct amdgpu_device* adev = psp->adev;
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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if (!ucode->fw)
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continue;
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if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
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psp_smu_reload_quirk(psp))
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continue;
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if (amdgpu_sriov_vf(adev) &&
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(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
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|| ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
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|| ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
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/*skip ucode loading in SRIOV VF */
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continue;
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ret = psp_prep_cmd_buf(ucode, psp->cmd);
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if (ret)
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return ret;
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ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
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psp->fence_buf_mc_addr, i + 3);
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if (ret)
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return ret;
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#if 0
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/* check if firmware loaded sucessfully */
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if (!amdgpu_psp_check_fw_loading_status(adev, i))
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return -EINVAL;
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#endif
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}
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return 0;
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}
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static int psp_load_fw(struct amdgpu_device *adev)
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{
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int ret;
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struct psp_context *psp = &adev->psp;
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if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
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goto skip_memalloc;
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psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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if (!psp->cmd)
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return -ENOMEM;
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ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
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AMDGPU_GEM_DOMAIN_GTT,
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&psp->fw_pri_bo,
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&psp->fw_pri_mc_addr,
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&psp->fw_pri_buf);
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if (ret)
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goto failed;
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ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&psp->fence_buf_bo,
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&psp->fence_buf_mc_addr,
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&psp->fence_buf);
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if (ret)
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goto failed_mem2;
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ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
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(void **)&psp->cmd_buf_mem);
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if (ret)
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goto failed_mem1;
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memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
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ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
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if (ret)
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goto failed_mem;
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ret = psp_tmr_init(psp);
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if (ret)
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goto failed_mem;
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ret = psp_asd_init(psp);
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if (ret)
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goto failed_mem;
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skip_memalloc:
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ret = psp_hw_start(psp);
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if (ret)
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goto failed_mem;
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ret = psp_np_fw_load(psp);
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if (ret)
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goto failed_mem;
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return 0;
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failed_mem:
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amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
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&psp->cmd_buf_mc_addr,
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(void **)&psp->cmd_buf_mem);
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failed_mem1:
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amdgpu_bo_free_kernel(&psp->fence_buf_bo,
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&psp->fence_buf_mc_addr, &psp->fence_buf);
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failed_mem2:
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amdgpu_bo_free_kernel(&psp->fw_pri_bo,
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&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
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failed:
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kfree(psp->cmd);
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psp->cmd = NULL;
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return ret;
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}
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static int psp_hw_init(void *handle)
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{
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int ret;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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mutex_lock(&adev->firmware.mutex);
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/*
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* This sequence is just used on hw_init only once, no need on
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* resume.
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*/
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ret = amdgpu_ucode_init_bo(adev);
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if (ret)
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goto failed;
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ret = psp_load_fw(adev);
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if (ret) {
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DRM_ERROR("PSP firmware loading failed\n");
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goto failed;
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}
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mutex_unlock(&adev->firmware.mutex);
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return 0;
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failed:
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adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
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mutex_unlock(&adev->firmware.mutex);
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return -EINVAL;
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}
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static int psp_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct psp_context *psp = &adev->psp;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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amdgpu_ucode_fini_bo(adev);
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psp_ring_destroy(psp, PSP_RING_TYPE__KM);
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amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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amdgpu_bo_free_kernel(&psp->fw_pri_bo,
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&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
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amdgpu_bo_free_kernel(&psp->fence_buf_bo,
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&psp->fence_buf_mc_addr, &psp->fence_buf);
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amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
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&psp->asd_shared_buf);
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amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
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(void **)&psp->cmd_buf_mem);
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kfree(psp->cmd);
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psp->cmd = NULL;
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return 0;
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}
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static int psp_suspend(void *handle)
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{
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int ret;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct psp_context *psp = &adev->psp;
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
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return 0;
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ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
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if (ret) {
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DRM_ERROR("PSP ring stop failed\n");
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return ret;
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}
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return 0;
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}
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|
static int psp_resume(void *handle)
|
|
{
|
|
int ret;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
struct psp_context *psp = &adev->psp;
|
|
|
|
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
|
return 0;
|
|
|
|
DRM_INFO("PSP is resuming...\n");
|
|
|
|
mutex_lock(&adev->firmware.mutex);
|
|
|
|
ret = psp_hw_start(psp);
|
|
if (ret)
|
|
goto failed;
|
|
|
|
ret = psp_np_fw_load(psp);
|
|
if (ret)
|
|
goto failed;
|
|
|
|
mutex_unlock(&adev->firmware.mutex);
|
|
|
|
return 0;
|
|
|
|
failed:
|
|
DRM_ERROR("PSP resume failed\n");
|
|
mutex_unlock(&adev->firmware.mutex);
|
|
return ret;
|
|
}
|
|
|
|
int psp_gpu_reset(struct amdgpu_device *adev)
|
|
{
|
|
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
|
return 0;
|
|
|
|
return psp_mode1_reset(&adev->psp);
|
|
}
|
|
|
|
static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
|
|
enum AMDGPU_UCODE_ID ucode_type)
|
|
{
|
|
struct amdgpu_firmware_info *ucode = NULL;
|
|
|
|
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
|
|
DRM_INFO("firmware is not loaded by PSP\n");
|
|
return true;
|
|
}
|
|
|
|
if (!adev->firmware.fw_size)
|
|
return false;
|
|
|
|
ucode = &adev->firmware.ucode[ucode_type];
|
|
if (!ucode->fw || !ucode->ucode_size)
|
|
return false;
|
|
|
|
return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
|
|
}
|
|
|
|
static int psp_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int psp_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs psp_ip_funcs = {
|
|
.name = "psp",
|
|
.early_init = psp_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = psp_sw_init,
|
|
.sw_fini = psp_sw_fini,
|
|
.hw_init = psp_hw_init,
|
|
.hw_fini = psp_hw_fini,
|
|
.suspend = psp_suspend,
|
|
.resume = psp_resume,
|
|
.is_idle = NULL,
|
|
.check_soft_reset = NULL,
|
|
.wait_for_idle = NULL,
|
|
.soft_reset = NULL,
|
|
.set_clockgating_state = psp_set_clockgating_state,
|
|
.set_powergating_state = psp_set_powergating_state,
|
|
};
|
|
|
|
static const struct amdgpu_psp_funcs psp_funcs = {
|
|
.check_fw_loading_status = psp_check_fw_loading_status,
|
|
};
|
|
|
|
static void psp_set_funcs(struct amdgpu_device *adev)
|
|
{
|
|
if (NULL == adev->firmware.funcs)
|
|
adev->firmware.funcs = &psp_funcs;
|
|
}
|
|
|
|
const struct amdgpu_ip_block_version psp_v3_1_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_PSP,
|
|
.major = 3,
|
|
.minor = 1,
|
|
.rev = 0,
|
|
.funcs = &psp_ip_funcs,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version psp_v10_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_PSP,
|
|
.major = 10,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &psp_ip_funcs,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version psp_v11_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_PSP,
|
|
.major = 11,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &psp_ip_funcs,
|
|
};
|