Lyude Paul d7787cc04e drm/nouveau/kms/nv50-: Fix clock checking algorithm in nv50_dp_mode_valid() ... While I thought I had this correct (since it actually did reject modes like I expected during testing), Ville Syrjala from Intel pointed out that the logic here isn't correct. max_clock refers to the max data rate supported by the DP encoder. So, limiting it to the output of ds_clock (which refers to the maximum dotclock of the downstream DP device) doesn't make any sense. Additionally, since we're using the connector's bpc as the canonical BPC we should use this in mode_valid until we support dynamically setting the bpp based on bandwidth constraints. https://lists.freedesktop.org/archives/dri-devel/2020-September/280276.html For more info. So, let's rewrite this using Ville's advice. v2: * Ville pointed out I mixed up the dotclock and the link rate. So fix that... * ...and also rename all the variables in this function to be more appropriately labeled so I stop mixing them up. * Reuse the bpp from the connector for now until we have dynamic bpp selection. * Use use DIV_ROUND_UP for calculating the mode rate like i915 does, which we should also have been doing from the start Signed-off-by: Lyude Paul <lyude@redhat.com> Fixes: 409d38139b ("drm/nouveau/kms/nv50-: Use downstream DP clock limits for mode validation") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lyude Paul <lyude@redhat.com> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2020-10-30 09:34:13 +10:00
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drm	drm/nouveau/kms/nv50-: Fix clock checking algorithm in nv50_dp_mode_valid()	2020-10-30 09:34:13 +10:00
host1x	drm next for 5.10-rc1	2020-10-15 10:46:16 -07:00
ipu-v3	treewide: Use fallthrough pseudo-keyword	2020-08-23 17:36:59 -05:00
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vga	vgaarb: mark vga_tryget static	2020-08-01 11:28:17 +02:00
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