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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/*
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* linux/arch/arm/mm/copypage-v4wb.c
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*
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* Copyright (C) 1995-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <asm/page.h>
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/*
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* ARMv4 optimised copy_user_page
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*
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* We flush the destination cache lines just before we write the data into the
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* corresponding address. Since the Dcache is read-allocate, this removes the
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* Dcache aliasing issue. The writes will be forwarded to the write buffer,
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* and merged as appropriate.
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*
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* Note: We rely on all ARMv4 processors implementing the "invalidate D line"
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* instruction. If your processor does not supply this, you have to write your
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* own copy_user_page that does the right thing.
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*/
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void __attribute__((naked))
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v4wb_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
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{
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asm("\
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stmfd sp!, {r4, lr} @ 2\n\
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mov r2, %0 @ 1\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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subs r2, r2, #1 @ 1\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
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bne 1b @ 1\n\
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mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
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ldmfd sp!, {r4, pc} @ 3"
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:
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: "I" (PAGE_SIZE / 64));
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}
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/*
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* ARMv4 optimised clear_user_page
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*
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* Same story as above.
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*/
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void __attribute__((naked))
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v4wb_clear_user_page(void *kaddr, unsigned long vaddr)
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{
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asm("\
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str lr, [sp, #-4]!\n\
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mov r1, %0 @ 1\n\
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mov r2, #0 @ 1\n\
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mov r3, #0 @ 1\n\
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mov ip, #0 @ 1\n\
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mov lr, #0 @ 1\n\
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1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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subs r1, r1, #1 @ 1\n\
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bne 1b @ 1\n\
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mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
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ldr pc, [sp], #4"
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:
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: "I" (PAGE_SIZE / 64));
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}
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struct cpu_user_fns v4wb_user_fns __initdata = {
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.cpu_clear_user_page = v4wb_clear_user_page,
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.cpu_copy_user_page = v4wb_copy_user_page,
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};
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